Asymmetrical transistor device and method of fabrication
View Patent ↗Embodiments of the invention provide an asymmetrical transistor device comprising a semiconductor substrate, a source region, a drain region and a channel region. The channel region is provided between the source and drain regions, the source, drain and channel regions being provided in the substrate. The device has a layer of a buried insulating medium provided below the source region and not below the drain region thereby forming an asymmetrical structure. The layer of buried insulating medium is provided in abutment with a lower surface of the source region.
1. A device comprising:
a substrate with upper and lower substrate portions, the substrate includes an asymmetrical transistor, wherein the asymmetrical transistor comprises
a gate disposed on the substrate having first and second sides,
a source disposed in the substrate on the first side of the gate,
a drain disposed in the substrate on the second side of the gate, wherein the source and drain are asymmetrical; and
a buried insulator layer disposed in the substrate on the first side and under the gate separating the upper and lower substrate portions while the upper substrate portion on the second side of the gate extends to the lower substrate portion.
2. The device in claim 1 wherein the source and drain comprise different source and drain depths.
3. The device in claim 2 wherein the source is disposed within the upper substrate portion and the drain has a drain depth which is deeper than a source depth of the source.
4. The device in claim 3 wherein the source depth is about a top surface of the buried insulator layer and the drain depth is below the top surface of the buried insulator layer.
5. The device in claim 4 wherein the buried insulator layer comprises an edge being about aligned with an edge of a gate sidewall spacer on the second side of the gate.
6. The device in claim 5 wherein the drain depth of the drain is in the lower portion of the substrate below a bottom surface of the buried insulator layer.
7. The device in claim 6 wherein the edge of the buried insulator layer comprises a recess underlying the gate sidewall spacer on the second side of the gate.
8. The device in claim 5 wherein the edge of the buried insulator layer comprises a recess underlying the gate sidewall spacer on the second side of the gate.
9. The device in claim 8 wherein the drain comprises a stressor.
10. The device in claim 9 wherein the stressor comprises a top stressor surface above a top surface of the substrate.
11. A device comprising:
a substrate with upper and lower substrate portions, the substrate includes an asymmetrical transistor, wherein the asymmetrical transistor comprises
a gate disposed on the substrate having first and second sides,
a first doped region disposed in the substrate on the first side of the gate, and a second doped region disposed in the substrate on the second side of the gate, wherein the first and second doped regions are asymmetrical; and
a buried insulator layer disposed in the substrate on the first side and under the gate separating the upper and lower substrate portions while the upper substrate portion on the second side of the gate extends to the lower substrate portion.
12. The device in claim 11 wherein the first and second doped regions comprise different depths.
13. The device in claim 12 wherein the first doped region comprises a source of the transistor and the second doped region comprises a drain of the transistor.
14. The device in claim 12 wherein the first doped region is disposed within the upper substrate portion and the second doped region has a second depth which is deeper than a first depth of the first doped region.
15. The device in claim 14 wherein the first doped region is disposed within the upper substrate portion and the second doped region has a second depth which is below a top surface of the buried insulator layer.
16. The device in claim 15 wherein the second depth is below a bottom surface of the buried insulator layer.
17. The device in claim 16 wherein the buried insulator layer comprises an edge being about aligned with an edge of a gate sidewall spacer on the second side of the gate.
18. The device in claim 14 wherein the second doped region comprises a stressor.
19. The device in claim 18 wherein the stressor comprises a top stressor surface above the substrate surface.
20. A device comprising:
a substrate with upper and lower substrate portions, the substrate includes an asymmetrical transistor, wherein the asymmetrical transistor comprises
a gate disposed on the substrate having first and second sides,
a first doped region disposed in the substrate on the first side of the gate, and a second doped region disposed in the substrate on the second side of the gate, wherein the first and second doped regions comprise different depths;
a buried insulator layer disposed in the substrate on the first side and under the gate separating the upper and lower substrate portions while the upper substrate portion on the second side of the gate extends to the lower substrate portion; and
wherein the first doped region is disposed in the upper substrate portion and the second doped region extends below a top surface of the buried insulator layer.