Latch-up robust PNP-triggered SCR-based devices

1. A method comprising:

providing a silicon control rectifier (SCR) region;

providing a PNP region proximate the SCR region and having a first n-well region, a first N+ region and a first P+ region in the first n-well region, and a second P+ region between the SCR region and the first n-well region, wherein the first N+ region is located between the first P+ region and the second P+ region;

coupling the first N+ region and the first P+ region to a power rail; and

coupling the second P+ region to a ground rail.

2. The method according to claim 1 , further comprising:

preventing latch mode of the SCR region until a pre-designated trigger threshold is satisfied by providing a first ESD current path from the power rail to the ground rail through the first n-well region of the PNP region.

3. The method according to claim 2 , further comprising:

providing the SCR region having a second n-well region, a second N+ region and a third P+ region in the second n-well region, and a third N+ region and a fourth P+ region between the second n-well region and the second P+ region;

coupling the second N+ region and the third P+ region to the power rail; and

coupling the third N+ region and the fourth P+ region to the ground rail.

4. The method according to claim 3 , further comprising:

providing a second ESD current path from the power rail to the ground rail through the second n-well region when the pre-designated trigger threshold is satisfied.

5. The method according to claim 3 , wherein the pre-designated trigger threshold includes a trigger current threshold of over 100 milliamps (mA).

6. The method according to claim 3 , further comprising:

providing a first distance between the third N+ region and the third P+ region; and

providing a second distance, that is different from the first distance, between the first and second P+ regions.

7. The method according to claim 6 , further comprising:

providing the first distance to be greater than the second distance.

8. The method according to claim 3 , further comprising:

coupling the second P+ region to the third N+ region and the fourth P+ region; and

coupling the first N+ region and the first P+ region to the second N+ region and the third P+ region.

9. A device comprising:

a silicon control rectifier (SCR) region; and

a PNP region proximate the SCR region and having a first n-well region, a first N+ region and a first P+ region in the first n-well region, and a second P+ region between the SCR region and the first n-well region, wherein the first N+ region is located between the first P+ region and the second P+ region the first N+ region and the first P+ region being coupled to a power rail, and the second P+ region being coupled to a ground rail.

10. The device according to claim 9 , further comprising:

a first ESD current path from the power rail to the ground rail through the first n-well region of the PNP region, wherein the device is configured to prevent latch mode of the SCR region based on the first ESD current path until a pre-designated trigger threshold is satisfied.

11. The device according to claim 10 , wherein the SCR region includes a second n-well region, a second N+ region and a third P+ region in the second n-well region, and a third N+ region and a fourth P+ region between the second n-well region and the second P+ region, and wherein the second N+ region and the third P+ region is coupled to the power rail, and the third N+ region and the fourth P+ region is coupled to the ground rail.

12. The device according to claim 11 , further comprising:

a second ESD current path from the power rail to the ground rail through the second n-well region when the pre-designated trigger threshold is satisfied.

13. The device according to claim 11 , wherein the pre-designated trigger threshold includes a trigger current threshold of over 100 milliamps (mA).

14. The device according to claim 11 , wherein the third N+ region and the third P+ region are separated by a first distance, and the first and second P+ regions are separated by a second distance different from the first distance.

15. The device according to claim 14 , wherein the first distance is greater than the second distance.

16. The device according to claim 11 , wherein the second P+ region is coupled to the third N+ region and the fourth P+ region, and the first N+ region and the first P+ region is coupled to the second N+ region and the third P+ region.

17. A method comprising:

providing a silicon control rectifier (SCR) region in a substrate;

providing a PNP region proximate the SCR region and having a first high voltage n-type double diffused (HVNDD) region, a first N+ region and a first P+ region in the first HVNDD region, and a second P+ region between the SCR region and the first HVNDD region, wherein the first N+ region is located between the first P+ region and the second P+ region; and

preventing latch mode of the SCR region until a pre-designated trigger current threshold is satisfied by providing a first ESD current path from a power rail to a ground rail through the first HVNDD region.

18. The method according to claim 17 , wherein the pre-designated trigger threshold includes a trigger current threshold of over 100 milliamps (mA).

19. The method according to claim 17 , further comprising:

providing the SCR region having a second HVNDD region, a second N+ region and a third P+ region in the second HVNDD region, and a third N+ region and a fourth P+ region between the second HVNDD region and the second P+ region;

coupling the first N+ region, the second N+ region, the first P+ region, and the third P+ region to the power rail; and

coupling the third N+ region, the second P+ region, and the fourth P+ region to the ground rail.

20. The method according to claim 19 , further comprising:

providing a first distance between the third N+ region and the third P+ region; and

providing a second distance, that is less than the first distance, between the first and second P+ regions.