Multi-level memory cells and methods for forming multi-level memory cells

1. A method of producing an integrated circuit with a multi-level memory cell comprising:

forming a gate insulator overlying a substrate;

forming a select gate overlying the gate insulator such that one multi-level memory cell includes one select gate;

forming a thin film storage layer overlying the select gate and the substrate, wherein the thin film storage layer comprises a plurality of nanocrystals;

forming a left control gate and a right control gate on opposite sides of the select gate and overlying the thin film storage layer such that the thin film storage layer is between the left control gate and the substrate, and the thin film storage layer is between the right control gate and the substrate;

forming a select gate hard mask overlying the select gate prior to forming the left control gate and the right control gate;

removing the select gate hard mask after forming the left control gate and the right control gate such that the left control gate and the right control gate extend above the select gate; and

forming a left implant and a right implant in the substrate such that the select gate, the left control gate, and the right control gate are positioned between the left implant and the right implant.

2. The method of claim 1 further comprising;

forming a left implant bit line electrically connected to the left implant and a right implant bit line electrically connected to the right implant.

3. The method of claim 1 further comprising:

forming a left control gate word line electrically connected to the left control gate;

forming a select gate word line electrically connected to the select gate; and

forming a right control gate word line electrically connected to the right control gate.

4. The method of claim 1 wherein forming the left control gate and the right control gate further comprises forming the left control gate and the right control gate with an approximately triangular shape.

5. The method of claim 4 wherein forming the left control gate and the right control gate further comprises:

depositing polysilicon overlying the select gate and the substrate; and

anisotropically etching the polysilicon.

6. The method of claim 1 further comprising:

leveling the left control gate and the right control gate by chemical mechanical planarization such that a control gate height is about the same as a select gate height.

7. The method of claim 1 further comprising:

forming a multi-level memory cell bank by forming a plurality of multi-level memory cells in a plurality of rows and columns.

8. The method of claim 1 further comprising:

forming an interlayer dielectric overlying the select gate, the left control gate, the right control gate, the left implant, and the right implant; and

forming a plurality of contacts through the interlayer dielectric, wherein the plurality of contacts comprises individual contacts electrically connected to each of the select gate, the left control gate, the right control gate, the left implant, and the right implant.

9. The method of claim 1 wherein forming the thin film storage layer further comprises:

forming a bottom dielectric layer;

forming the plurality of nanocrystals overlying the bottom dielectric layer; and

forming a top dielectric layer overlying the plurality of nanocrystals.

10. The method of claim 1 further comprising:

forming logic gate spacers adjacent to the left control gate and the right control gate.

11. A method of forming an integrated circuit with a multi-level memory cell bank comprising a plurality of multi-level memory cells, the method comprising:

forming a plurality of select gates overlying a substrate in a plurality of rows and a plurality of columns;

forming a select gate hard mask overlying each select gate;

forming a thin film storage layer overlying the substrate and the plurality of select gates, wherein the thin film storage layer comprises a plurality of nanocrystals;

forming a left control gate and a right control gate overlying the thin film storage layer and on opposite sides of each select gate, wherein the left control gate and the right control gate are self aligned with the select gate, and wherein the left control gate and the right control gate have an approximately triangular shape that extends above the select gate to the select gate hard mask;

removing the select gate hard mask such that a control gate height is larger than a select gate height

forming a left implant and a right implant in the substrate on opposite sides of each left control gate and right control gate, wherein one multi-level memory cell comprises one select gate, one left control gate, one right control gate, one left implant and one right implant, and wherein the select gate, left control gate, and right control gate are between the left implant and the right implant;

forming a left control gate word line, a right control gate word line, and a select gate word line, wherein the left control gate word line, the right control gate word line, and the select gate word line are electrically connected to the left control gate, the right control gate, and the select gate, respectively, of each multi-level memory cell in one column; and

forming a left implant bit line and a right implant bit line, wherein the left implant bit line and the right implant bit line are electrically connect to the left implant and the right implant, respectively, of each multi-level memory cell in one row.

12. The method of claim 11 wherein forming the left control gate and the right control gate further comprises:

depositing polysilicon overlying the select gate and the substrate; and

anisotropically etching the polysilicon.

13. The method of claim 11 wherein forming the thin film storage layer further comprises:

forming a bottom dielectric layer;

forming the plurality of nanocrystals overlying the bottom dielectric layer; and

forming a top dielectric layer overlying the plurality of nanocrystals.

14. The method of claim 11 further comprising:

forming a gate insulator overlying the substrate prior to forming the plurality of select gates such that the gate insulator is positioned between the substrate and each select gate.

15. The method of claim 11 further comprising:

leveling the left control gate and the right control gate with the select gate by chemical mechanical planarization such that the control gate height is about the same as the select gate height.

16. The method of claim 11 further comprising:

removing the thin film storage layer from over the plurality of select gates prior to electrically connecting the select gate word line with the select gates.

17. The method of claim 11 further comprising:

forming logic gate spacers adjacent to the left control gate and the right control gate.