Compact RRAM device and methods of making same

1. A RRAM device, comprising:

a gate electrode;

a conductive sidewall spacer; and

at least one variable resistance material layer positioned between said gate electrode and said conductive sidewall spacer wherein at least a portion of said at least one variable resistance material layer is formed on and in contact with a surface of a semiconducting substrate and wherein said portion of said at least one variable resistance material layer is positioned between said substrate and a bottom of said conductive sidewall spacer.

2. The device of claim 1 , further comprising a liner layer positioned between said gate electrode and said at least one variable resistance material layer.

3. The device of claim 1 , wherein said at least one variable resistance material layer has a generally L-shaped configuration.

4. The device of claim 1 , wherein said at least one variable resistance material layer is comprised of at least one of the following materials: a perovskite material, a colossal magnetoresistive (CMR) material, a high temperature superconducting (HTSC) material, Pr. .07 Ca. 0.3 MnO 3 (PCMO), Gd 0.7 CaO 0.3 BaCo 2 O 5+5 , a transition metal oxide, hafnium oxide, titanium oxide, nickel oxide, tungsten oxide, tantalum oxide, copper oxide, a manganite, a titanate, STO:Cr, a zirconate, SZO:Cr, Ca 2 Nb 2 O 7 :Cr, Ta 2 O 5 :Cr, a high Tc superconductor and YBCO.

5. The device of claim 1 , wherein said conductive sidewall spacer consists of a metal.

6. The device of claim 1 , wherein said conductive sidewall spacer is comprised of a variable resistance material.

7. A RRAM device, comprising:

a gate electrode;

a conductive sidewall spacer; and

at least one variable resistance material layer wherein at least a first portion of said at least one variable resistance material layer is positioned between said gate electrode and said conductive sidewall spacer, and wherein a second portion of said at least one variable resistance material layer is formed on and in contact with a surface of a semiconducting substrate, wherein said second portion of said at least one variable resistance material layer is positioned between said substrate and a bottom of said conductive sidewall spacer.

8. The device of claim 7 , further comprising a liner layer positioned between said gate electrode and said at least one variable resistance material layer.

9. The device of claim 7 , wherein said at least one variable resistance material layer has a generally L-shaped configuration.

10. The device of claim 7 , wherein said at least one variable resistance material layer is comprised of at least one of the following materials: a perovskite material, a colossal magnetoresistive (CMR) material, a high temperature superconducting (HTSC) material, Pr. 0.7 Ca. 0.3 MnO 3 (PCMO), Gd 0.7 CaO 0.3 BaCo 2 O 5+5 , a transition metal oxide, hafnium oxide, titanium oxide, nickel oxide, tungsten oxide, tantalum oxide, copper oxide, a manganite, a titanate, STO:Cr, a zirconate, SZO:Cr, Ca 2 Nb 2 O 7 :Cr, Ta 2 O 5 :Cr, a high Tc superconductor and YBCO.

11. A RRAM device, comprising:

a first unit cell and a second unit cell formed in and above a semiconducting substrate, wherein each of said unit cells comprises:

a gate electrode;

a conductive sidewall spacer; and

at least one variable resistance material layer positioned between said gate electrode and said conductive sidewall spacer;

an isolation structure positioned at least partially in said substrate, said isolation structure electrically isolating said first and second unit cells; and

at least one conductive contact that is physically and conductively coupled to said conductive sidewall spacer on said first unit cell and said conductive sidewall spacer on said second unit cell.

12. The device of claim 11 , wherein said conductive sidewall spacer on said first unit cell and said conductive sidewall spacer on said second unit cell are formed such that they physically and conductively contact one another at a contact region.

13. The device of claim 11 , further comprising a conductive contact structure that is physically and conductively coupled to said conductive sidewall spacer on said first unit cell and said conductive sidewall spacer on said second unit cell, said conductive contact structure being comprised of the same material as said conductive sidewall spacers.

14. The device of claim 11 wherein said at least one conductive contact is a contact to electrical ground or a relatively low voltage.

15. A RRAM device, comprising:

a gate electrode;

a sidewall spacer consisting of a variable resistance material; and

at least one conductive contact that is physically and conductively coupled to said sidewall spacer.

16. The device of claim 15 , further comprising a liner layer positioned between said gate electrode and said sidewall spacer.

17. The device of claim 15 , wherein said variable resistance material is comprised of at least one of the following materials: a perovskite material, a colossal magnetoresistive (CMR) material, a high temperature superconducting (HTSC) material, Pr. 0.7 Ca. 0.3 MnO 3 (PCMO), Gd 0.7 CaO 0.3 BaCo 2 O 5+5 , a transition metal oxide, hafnium oxide, titanium oxide, nickel oxide, tungsten oxide, tantalum oxide, copper oxide, a manganite, a titanate, STO:Cr, a zirconate, SZO:Cr, Ca 2 Nb 2 O 7 :Cr, Ta 2 O 5 :Cr, a high Tc superconductor and YBCO.

18. The device of claim 15 , wherein a substantially horizontal portion of said sidewall spacer is formed on and in contact with a surface of a semiconducting substrate and a substantially vertical portion of said sidewall spacer is formed on and in contact with said gate electrode.

19. A RRAM device, comprising:

a first unit cell and a second unit cell formed in and above a semiconducting substrate, wherein each of said unit cells comprises:

a gate electrode; and

a sidewall spacer consisting of a variable resistance material;

at least one conductive contact that is physically and conductively coupled to said sidewall spacer in said first unit cell and said sidewall spacer in said second unit cell; and

an isolation structure positioned at least partially in said substrate, said isolation structure electrically isolating said first and second unit cells.

20. The device of claim 19 , wherein said sidewall spacers in said first and second unit cells are formed such that they contact one another at a contact region.

21. The device of claim 19 , wherein said at least one conductive contact is a contact to electrical ground or a relatively low voltage.

22. A RRAM device, comprising:

a first unit cell and a second unit cell formed in and above a semiconducting substrate, wherein each of said unit cells comprises:

a gate electrode;

a conductive sidewall spacer;

at least one variable resistance material layer positioned between said gate electrode and said conductive sidewall spacer; and

an isolation structure positioned at least partially in said substrate, said isolation structure electrically isolating said first and second unit cells, wherein said conductive sidewall spacer on said first unit cell and said conductive sidewall spacer on said second unit cell are formed such that they physically and conductively contact one another at a contact region.

23. A RRAM device, comprising:

a first unit cell and a second unit cell formed in and above a semiconducting substrate, wherein each of said unit cells comprises:

a gate electrode;

a conductive sidewall spacer;

at least one variable resistance material layer positioned between said gate electrode and said conductive sidewall spacer;

an isolation structure positioned at least partially in said substrate, said isolation structure electrically isolating said first and second unit cells; and

a conductive contact structure that is physically and conductively coupled to said conductive sidewall spacer on said first unit cell and said conductive sidewall spacer on said second unit cell, said conductive contact structure being comprised of the same material as said conductive sidewall spacers.