Methods of forming CMOS transistors using tensile stress layers and hydrogen plasma treatment

1. A method of forming an integrated circuit device, comprising:

forming a PMOS transistor having a SiGe channel region therein, said forming a PMOS transistor comprising adjusting a position of a substrate such that a crystallographic orientation of the SiGe channel region formed in the substrate is parallel to a <100> crystallographic orientation of the substrate;

exposing source and drain regions of the PMOS transistor to a hydrogen plasma; and

forming a tensile stress layer on the PMOS transistor, which applies tensile stress to the SiGe channel region, after said exposing.

2. The method of claim 1 , wherein said forming comprises forming a silicon nitride layer having a net tensile stress therein on the PMOS transistor.

3. The method of claim 1 , wherein said exposing is preceded by depositing a tensile stress liner on the PMOS transistor; and wherein said exposing comprises exposing the tensile stress liner to the hydrogen plasma.

4. The method of claim 3 , wherein the tensile stress liner is thinner than the tensile stress layer.

5. The method of claim 3 , further comprising exposing at least a portion of the PMOS transistor to a hydrogen plasma before said depositing.

6. The method of claim 4 , wherein the tensile stress liner is deposited to a thickness of greater than 0 Å and less than 100 Å.

7. The method of claim 1 , wherein said exposing is performed in-situ with said forming the tensile stress layer on the PMOS transistor.

8. The method of claim 1 , wherein forming a PMOS transistor comprises:

selectively etching a surface of the substrate to define a recess therein; and

epitaxially growing a silicon germanium region in the recess.

9. A method of forming an integrated circuit device, comprising:

forming a plurality of MOS transistors adjacent a surface of a semiconductor substrate, said MOS transistors comprising PMOS transistors having SiGe channel regions and NMOS transistors having silicon channel regions, said SiGe channel regions having crystallographic orientations that are parallel to a <100> crystallographic orientation of the semiconductor substrate;

exposing source and drain regions of the PMOS and NMOS transistors to a hydrogen plasma; and

forming an electrically insulating tensile stress layer on the PMOS and NMOS transistors, which applies tensile stress to the SiGe channel regions and silicon channel regions, after said exposing.

10. The method of claim 9 , wherein said forming comprises forming a silicon nitride layer having a net tensile stress therein on the MOS transistors.

11. The method of claim 9 , wherein said exposing is preceded by depositing a tensile stress liner on the MOS transistors; and wherein said exposing comprises exposing the tensile stress liner to the hydrogen plasma.

12. The method of claim 11 , wherein the tensile stress liner is thinner than the tensile stress layer.

13. The method of claim 11 , further comprising exposing the PMOS and NMOS transistors to a hydrogen plasma before said depositing.

14. A method of forming an integrated circuit device, comprising:

forming a PMOS transistor having a SiGe channel region therein,

said forming a PMOS transistor comprising adjusting a position of a substrate such that a crystallographic orientation of the SiGe channel region formed in the substrate is parallel to a <100> crystallographic orientation of the substrate;

exposing at least a portion of the PMOS transistor to a hydrogen plasma; and

forming a silicon nitride layer having a net tensile stress on the PMOS transistor, which applies tensile stress to the SiGe channel region, wherein said forming the silicon nitride layer comprises performing a plasma enhanced chemical vapor deposition (PECVD) using SiN 4 gas supplied at a rate in a range of about 10 to about 100 sccm, NH 3 gas supplied at a rate in a range of about 10 to about 100 sccm, and N 2 gas supplied at a rate in a range of about 1 to about 5 slm (standard liters per minute) with a RF power setting in a range of about 50 watts to about 1000 watts at a process temperature in a range of about 400° C. to about 500° C.

15. The method of claim 14 , wherein said exposing comprises exposing source and drain regions of the PMOS transistor to the hydrogen plasma.

16. The method of claim 15 , wherein said forming the silicon nitride layer follows said exposing.

17. The method of claim 14 , wherein said exposing is performed in-situ with said forming the silicon nitride layer.