MOS with recessed lightly-doped drain
View Patent ↗LDD regions are provided with high implant energy in devices with reduced thickness poly-silicon layers and source/drain junctions. Embodiments include forming an oxide layer on a substrate surface, forming a poly-silicon layer over the oxide layer, forming first and second trenches through the oxide and poly-silicon layers and below the substrate surface, defining a gate region therebetween, implanting a dopant in a LDD region through the first and second trenches, forming spacers on opposite side surfaces of the gate region and extending into the first and second trenches, and implanting a dopant in a source/drain region below each of the first and second trenches.
1. A device comprising:
a substrate having a surface;
a gate region on the substrate surface;
a recess in the substrate on each side of the gate region;
a source/drain region in the substrate, below each recess;
a spacer on each side of the gate region and extending down into the recess;
a second gate region on the substrate surface; and
a second source/drain region extending downward from the substrate surface, on each side of the second gate region, wherein:
the second source/drain region is positioned higher in the substrate surface than the first source/drain region, and
the gate region has a first uppermost surface and the second gate region has a second uppermost surface, and the first and second uppermost surfaces are at substantially the same height.
2. The device according to claim 1 , wherein the recess has a depth of 10 nm to 200 nm and a width of 0.2 μm to 0.6 μm.
3. The device according to claim 1 , wherein each spacer comprises a portion in the recess, the device further comprising a lightly-doped drain (LDD) region in the substrate below each spacer and extending around the portion of the spacer in the recess and toward the gate region.
4. The device according to claim 1 , further comprising:
an oxide layer in the gate region; and
a poly-silicon layer in the gate region.
5. The device according to claim 4 , wherein the oxide layer has a thickness of 5 nm to 15 nm.
6. The device according to claim 5 , wherein the poly-silicon layer has a thickness of 50 nm to 300 nm.
7. The device according to claim 1 , further comprising a silicide in each recess, over the first source/drain regions.
8. The device according to claim 1 , further comprising:
second spacers on opposite sides of the second gate region, formed on the substrate surface.
9. The device according to claim 8 , further comprising:
a first oxide layer and a first poly-silicon layer in the first gate region; and
a second oxide layer and a second poly-silicon layer in the second gate region,
wherein the first oxide layer is thicker than the second oxide layer.
10. The device according to claim 9 , wherein each first spacer comprises a portion in the recess, the device further comprising:
a first LDD region in the substrate below each first spacer and extending around the portion of the first spacer in the recess and toward the first gate region; and
a second LDD region below each second spacer and extending laterally under the second gate region.
11. The device according to claim 8 , further comprising first, second, and third shallow trench isolation (STI) regions in the substrate, wherein the first and second STI regions are adjacent the first source/drain regions, laterally away from the first gate region, and the second and third STI regions are adjacent the second source/drain regions, laterally away from the second gate region.
12. The device according to claim 11 , further comprising:
a first well region in the substrate between the first and second STI regions; and
a second well region in the substrate between the second and third STI regions.
13. The device according to claim 12 , wherein each of the first and second well regions has a depth of 50 nm to 2000 nm.
14. A device comprising:
a substrate having a surface;
first and second well regions formed in the substrate, below the substrate surface;
a first gate region on the substrate surface over the first well region, the first gate region comprising a first oxide layer and a first poly-silicon layer;
a second gate region on the substrate surface over the second well region, the second gate region comprising a second oxide layer and a second poly-silicon layer, wherein the first oxide layer is thicker than the second oxide layer;
a recess in the first well region on each side of the first gate region;
a first source/drain region in the first well region, below each recess;
a second source/drain region in the second well region on each side of the second gate region, extending downward from the substrate surface, the second source/drain region is positioned higher in the substrate surface than the first source/drain region;
a first spacer on each side of the first gate region and extending down into the recess; and
a second spacer on each side of the second gate region and extending down to the substrate surface,
the first gate region has a first uppermost surface and the second gate region has a second uppermost surface, and the first and second uppermost surfaces are at substantially the same height.
15. The device according to claim 14 , wherein each recess has a depth of 10 nm to 200 nm and a width of 0.2 μm to 0.6 μm.
16. The device according to claim 14 , wherein the first oxide layer has a thickness of 5 nm to 15 nm, and the second oxide layer has a thickness of 1 nm to 3 nm.
17. The device according to claim 14 , further comprising a first silicide in each recess, over the first source/drain regions and a second silicide over each second source/drain region.
18. The device according to claim 14 , wherein each first spacer comprises a portion in the recess, the device further comprising:
a first LDD region in the substrate below each first spacer and extending around the portion of the first spacer in the recess and toward the first gate region; and
a second LDD region below each second spacer and extending laterally under the second gate region.
19. The device according to claim 14 , further comprising first, second, and third shallow trench isolation (STI) regions in the substrate, wherein the first and second STI regions bound the first well region, and the second and third STI regions bound the second region.
20. A device comprising:
a substrate having a surface;
first and second well regions formed in the substrate, below the substrate surface;
a first gate region on the substrate surface over the first well region, the first gate region comprising a first oxide layer having a thickness of 5 nm to 15 nm and a first poly-silicon layer;
a second gate region on the substrate surface over the second well region, the second gate region comprising a second oxide layer having a thickness of 1 nm to 3 nm and a second poly-silicon layer;
a recess, having a depth of 10 nm to 200 nm and a width of 0.2 μm to 0.6 μm, in the first well region on each side of the first gate region;
a first source/drain region in the first well region, below each recess;
a second source/drain region in the second well region on each side of the second gate region, extending downward from the substrate surface, wherein the second source/drain region is positioned higher in the substrate surface than the first source/drain region;
a first spacer on each side of the first gate region and extending down into the recess, each first spacer comprising a portion in the recess;
a second spacer on each side of the second gate region and extending down to the substrate surface;
a first LDD region in the substrate below each first spacer and extending around the portion of the first spacer in the recess and toward the first gate region; and
a second LDD region below each second spacer and extending laterally under the second gate region,
the first gate region has a first uppermost surface and the second gate region has a second uppermost surface, and the first and second uppermost surfaces are at substantially the same height.