Integrated circuits with programmable memory and methods for producing the same
View Patent ↗Methods of producing integrated circuits and integrated circuits produced by those methods are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming first and second shallow trench isolations within a substrate, where the first and second shallow trench isolations have an initial shallow trench height. A base well is formed in the substrate, where the base well is positioned between the first and second shallow trench isolations. A gate dielectric is formed overlying the base well, and a floating gate is formed overlying the gate dielectric. An initial shallow trench height is reduced to a reduced shallow trench height shorter than the initial shallow trench height after the floating gate is formed.
1. A method of producing an integrated circuit comprising:
forming a first shallow trench isolation and a second shallow trench isolation within a substrate, wherein the first shallow trench isolation comprises an initial shallow trench height;
forming a base well in the substrate, wherein the base well is positioned between the first shallow trench isolation and the second shallow trench isolation;
forming a gate dielectric overlying the base well;
forming a floating gate overlying the gate dielectric, where the floating gate comprises a side surface, and where a portion of the side surface is covered by the first shallow trench isolation and an exposed portion of the side surface is exposed; and
reducing the initial shallow trench height to a reduced shallow trench height shorter than the initial shallow trench height after forming the floating gate.
2. The method of claim 1 wherein reducing the initial shallow trench height comprises exposing the first shallow trench isolation to a wet etch.
3. The method of claim 1 wherein the exposed portion of the side surface of the floating gate is not covered by the first or second shallow trench isolation.
4. The method of claim 1 further comprising:
forming a flash dielectric overlying the floating gate and the first shallow trench isolation.
5. The method of claim 4 wherein forming the flash dielectric comprises forming the flash dielectric comprising a first flash dielectric layer, a second flash dielectric layer, and a third flash dielectric layer.
6. The method of claim 5 wherein forming the flash dielectric comprises forming the first flash dielectric layer comprising silicon dioxide, forming the second flash dielectric layer comprising silicon nitride, and forming the third flash dielectric layer comprising silicon dioxide.
7. The method of claim 1 wherein reducing the initial shallow trench height comprises reducing the initial shallow trench height by from about 50 angstroms to about 300 angstroms.
8. The method of claim 1 further comprising:
forming a select gate overlying the substrate and adjacent to the floating gate.
9. The method of claim 8 further comprising:
forming a source in the substrate;
forming a drain in the substrate, wherein a channel is defined within the substrate between the source and the drain, and wherein the select gate and the floating gate overlie the channel.
10. The method of claim 1 further comprising:
optimizing the reduced shallow trench height.
11. The method of claim 1 wherein:
reducing the initial shallow trench height comprises reducing the initial shallow trench height to the reduced shallow trench height, wherein the initial shallow trench height and the reduced shallow trench height are measured from a first top surface of the first shallow trench isolation to a substrate bottom surface; and
forming the floating gate comprises forming the floating gate with a floating gate bottom height measured from a floating gate lowest point to the substrate bottom surface, and wherein the reduced shallow trench height is from about 10 angstroms to about 200 angstroms greater than the floating gate bottom height.
12. A method of producing an integrated circuit comprising:
forming a first shallow trench isolation and a second shallow trench isolation within a substrate;
forming a base well in the substrate, wherein the base well is positioned between the first shallow trench isolation and the second shallow trench isolation;
forming a gate dielectric overlying the base well;
forming a floating gate overlying the gate dielectric, wherein the floating gate has a side surface with an exposed surface area, and wherein a portion of the side surface is covered by the first shallow trench isolation; and
increasing the exposed surface area of the side surface after forming the floating gate.
13. The method of claim 12 further comprising:
forming a flash dielectric overlying the first shallow trench isolation and the floating gate.
14. The method of claim 13 further comprising forming a control gate overlying the flash dielectric.
15. The method of claim 14 wherein increasing the exposed surface area of the side surface comprises increasing a control gate to floating gate coupling ratio.
16. The method of claim 14 further comprising:
forming a select gate overlying the substrate, wherein the select gate is adjacent to the floating gate and the select gate is adjacent to the control gate.
17. The method of claim 16 further comprises:
forming a source and a drain in the substrate such that a channel is defined in the substrate between the source and the drain, wherein the select gate and the floating gate overlie the channel.
18. The method of claim 12 wherein increasing the exposed surface area of the side surface comprises reducing an initial shallow trench height.
19. The method of claim 12 wherein the exposed surface area is a surface area of an exposed portion of the side surface of the floating gate that is not covered by the first or second shallow trench isolation.