Structure and methods of improving reliability of non-volatile memory devices
View Patent ↗A method includes forming a patterned gate stack for a memory device, the patterned gate stack including a gate insulation layer, a charge storage layer, a blocking insulation layer and a gate electrode, the gate insulation layer and the blocking insulation layer having an initial width. An etching process is performed on the patterned gate stack to selectively remove at least a portion of each of the gate insulation layer and the blocking insulation layer, the etching process reducing a width of each of the gate insulation layer and the blocking insulation layer from the initial width to a final width. After performing the etching process, at least one material layer is formed proximate sidewalls of the patterned gate stack, the at least one material layer laterally confining each of the gate insulation layer, the charge storage layer, the blocking insulation layer, and the gate electrode.
1. A method, comprising:
forming a patterned gate stack for a memory device, said patterned gate stack comprising a gate insulation layer, a charge storage layer, a blocking insulation layer and a gate electrode, said gate insulation layer and said blocking insulation layer having an initial width;
performing an etching process on said patterned gate stack to selectively remove at least a portion of each of said gate insulation layer and said blocking insulation layer, said etching process reducing a width of each of said gate insulation layer and said blocking insulation layer from said initial width to a final width; and
after performing said etching process, forming at least one material layer proximate sidewalls of said patterned gate stack, said at least one material layer laterally confining each of said gate insulation layer, said charge storage layer, said blocking insulation layer, and said gate electrode.
2. The method of claim 1 , wherein said at least one material layer formed proximate said sidewalls of said patterned gate stack defines gaps proximate opposite ends of each of said gate insulation layer and said blocking insulation layer.
3. The method of claim 2 , wherein each of said gaps is substantially free of solid material.
4. The method of claim 1 , wherein said final width is approximately 70-90% of said initial width.
5. The method of claim 1 , wherein forming at least one material layer proximate said sidewalls of said patterned gate stack comprises forming a sidewall spacer element.
6. The method of claim 1 , wherein said gate insulation layer and said blocking insulation layer comprise a first material and said charge storage layer comprises a second material that is different than said first material.
7. The method of claim 6 , wherein said first material is one of silicon dioxide and silicon nitride and said second material is one of silicon nitride and polysilicon.
8. A method, comprising:
forming a gate stack of a memory device, said gate stack comprising a gate insulation layer having first and second edges, a charge storage layer formed above said gate insulation layer and having first and second edges, a blocking insulation layer formed above said charge storage layer and having first and second edges, and a gate electrode formed above said blocking insulation layer and having first and second sidewalls, wherein said first edge of said charge storage layer is laterally and inwardly offset from said first edge of said gate insulation layer, said first edge of said blocking insulation layer, and said first sidewall;
forming a first spacer adjacent to said first sidewall and said respective first edges of said gate insulation layer, said charge storage layer, and said blocking insulation layer, said gate insulation layer, said blocking insulation layer, and said first spacer at least partially defining a first gap that is positioned laterally adjacent to at least said first edge of said charge storage layer; and
forming a second spacer adjacent to said second sidewall and said respective second edges of said gate insulation layer, said charge storage layer, and said blocking insulation layer, said first and second spacers laterally confining each of said gate insulation layer, said charge storage layer, said blocking insulation layer, and said gate electrode.
9. The method of claim 8 , wherein said gate stack is formed so that said respective first edges of said gate insulation layer and said blocking insulation layer are substantially aligned with said first sidewall.
10. The method of claim 9 , further comprising, prior to forming said first spacer, forming a layer of insulating material on said substantially aligned first edges and first sidewall, said layer of insulating material substantially filling said first gap.
11. The method of claim 9 , wherein said first spacer is formed on and in contact with said substantially aligned first edges and first sidewall, and wherein after forming said first spacer said first gap is substantially free of solid material.
12. The method of claim 9 , wherein said gate stack is formed so that said respective second edges of said gate insulation layer, said charge storage layer, and said blocking insulation layer are substantially aligned with said second sidewall and said second spacer is formed on and in contact with said substantially aligned second edges and second sidewall.
13. The method of claim 9 , wherein said gate stack is formed so that said second edge of said charge storage layer is laterally and inwardly offset from said second edge of said gate insulation layer, said second edge of said blocking insulation layer, and said second sidewall, and wherein said gate insulation layer, said blocking insulation layer, and said second spacer at least partially define a second gap that is positioned laterally adjacent to at least said second edge of said charge storage layer.
14. The method of claim 13 , wherein said first and second gaps are substantially free of solid material.
15. The method of claim 13 , further comprising:
prior to forming said first spacer, forming a first layer of insulating material on said substantially aligned first edges and first sidewall, said first layer of insulating material substantially filling said first gap; and
prior to forming said second spacer, forming a second layer of insulating material on said substantially aligned second edges and second sidewall, said second layer of insulating material substantially filling said second gap.
16. A method for forming a memory device, the method comprising:
forming a gate insulation layer having a first width above a semiconducting substrate;
forming a charge storage layer having a second width above said gate insulation layer, said second width being less than said first width;
forming a blocking insulation layer having said first width above said charge storage layer;
forming a gate electrode having said first width above said blocking insulation layer; and
forming a sidewall spacer adjacent to and laterally confining each of said gate insulation layer, said charge storage layer, said blocking insulation layer, and said gate electrode, wherein said sidewall spacer, said gate insulation layer, and said blocking insulation layer at least partially define a first gap that is positioned laterally adjacent to at least a first edge of said charge storage layer.
17. The method of claim 16 , wherein said sidewall spacer, said gate insulation layer, and said blocking insulation layer at least partially define a second gap that is positioned laterally adjacent to at least a second edge of said charge storage layer.
18. The method of claim 16 , wherein said first width is approximately 70-90% of said second width.
19. The method of claim 16 , wherein said charge storage layer comprises silicon nitride and said gate electrode comprises polysilicon.
20. The method of claim 16 , wherein said charge storage layer and said gate electrode comprise a same material.