Integrated circuit system employing an elevated drain
View Patent ↗A method for manufacturing an integrated circuit system that includes: providing a substrate including an active device; forming a drift region in the substrate, the drift region bounded in part by a top surface of the substrate and spaced apart from a source; and forming a drain above the drift region.
1. A method for manufacturing an integrated circuit system comprising:
providing a substrate including an active device;
forming a drift region in the substrate, the drift region bounded in part by a top surface of the substrate and spaced apart from a source; and
forming a drain directly on the drift region and not within the substrate wherein the drain is formed completely above the top surface of the substrate.
2. The method as claimed in claim 1 wherein:
providing the active device includes providing an NMOS device.
3. The method as claimed in claim 1 wherein:
forming the drain inlcudes an epitaxial growth process.
4. The method as claimed in claim 1 wherein:
forming the drain inlcudes depositing a semiconducting material.
5. The method as claimed in claim 1 wherein:
forming the drain above the drift region alters the substrate current, the parasitic capacitance, or the on-state resistance of the active device.
6. A method for manufacturing an integrated circuit system comprising:
providing a substrate;
forming a drift region in the substrate, the drift region bounded in part by a top surface of the substrate;
forming a drain directly on the drift region and not within the substrate wherein the drain is formed completely above the top surface of the substrate;
forming a source in the substrate and spaced apart from the drift region;
forming a gate dielectric, a gate, and a spacer above the substrate; and
forming an electrical contact.
7. The method as claimed in claim 6 wherein:
forming the drain and the gate includes forming each structure to be substantially coplanar with the other.
8. The method as claimed in claim 6 wherein:
forming the drain above the drift region includes forming the drain on the substrate.
9. The method as claimed in claim 6 wherein:
forming the gate includes overlapping a portion of the source and the drift region with the gate.
10. The method as claimed in claim 6 wherein:
forming the electrical contact includes one of the electrical contact formed over the source and aligned to the spacer.
11. An integrated circuit system comprising:
a substrate including an active device;
a drift region in the substrate, the drift region bounded in part by a top surface of the substrate and spaced apart from a source; and
a drain directly on the drift region and not within the substrate wherein the drain is formed completely above the top surface of the substrate.
12. The system as claimed in claim 11 wherein:
the active device includes an NMOS device.
13. The system as claimed in claim 11 wherein:
the drain inlcudes an epitaxial material.
14. The system as claimed in claim 11 wherein:
the drain inlcudes a semiconducting material.
15. The system as claimed in claim 11 wherein:
the location of the drain above the drift region alters the substrate current, the parasitic capacitance, or the on-state resistance of the active device.
16. The system as claimed in claim 11 wherein:
the substrate includes a lightly doped region.
17. The system as claimed in claim 11 wherein:
the drain and the gate are substantially coplanar with each other.
18. The system as claimed in claim 11 wherein:
the drain is on the substrate.
19. The system as claimed in claim 11 further comprising:
a gate of the active device that overlaps a portion of the source and the drift region.
20. The system as claimed in claim 11 further comprising:
an electrical contact over the source and aligned to a spacer.