Integrated circuits having tunnel transistors and methods for fabricating the same
View Patent ↗Integrated circuits including tunnel transistors and methods for fabricating such integrated circuits are provided. An exemplary method for fabricating an integrated device includes forming a lower source/drain region in and/or over a semiconductor substrate. The method forms a channel region overlying the lower source/drain region. The method also forms an upper source/drain region overlying the channel region. The method includes forming a gate structure beside the channel region.
1. A method for fabricating an integrated circuit, the method comprising:
etching a semiconductor material to form a fin structure having a horizontal top surface and a vertical side surface formed from the semiconductor material and to form an exposed horizontal surface of the semiconductor material adjacent the vertical side surface of the fin structure;
epitaxially growing a pocket region of semiconductor material on the vertical side surface formed from the semiconductor material and directly on the exposed horizontal surface of the semiconductor material and preventing growth of the pocket region on the top surface of the fin structure with a mask on the top surface of the fin structure; and
forming a gate structure adjacent the pocket region, wherein a tunnel transistor is formed by the fin structure, the pocket region and the gate structure.
2. The method of claim 1 further comprising forming a source region and a channel region in the semiconductor material before etching the semiconductor material to form the fin structure.
3. The method of claim 1 further comprising forming a source region, a channel region, and a drain region in the semiconductor material before etching the semiconductor material to form the fin structure.
4. The method of claim 1 further comprising forming a source region doped with a first type of dopant, a channel region, and a drain region doped with a second type of dopant in the semiconductor material before etching the semiconductor material to form the fin structure, wherein epitaxially growing the pocket region of semiconductor material comprises epitaxially growing a pocket region of semiconductor material doped with the second type of dopant.
5. The method of claim 1 further comprising forming a source/drain region in the semiconductor material before etching the semiconductor material to form the fin structure, wherein a portion of the vertical side surface of the fin structure defines a side surface of an upper portion of the source/drain region and wherein a portion of the exposed horizontal surface of the semiconductor material defines an upper surface of a lower portion of the source/drain region.