MULTI-TIME PROGRAMMABLE MEMORY
A device is disclosed. The device includes a substrate and a fin structure disposed on the substrate. The fin structure serves as a common body of n transistors. The transistors include separate charge storage layers and gate dielectric layers. The charge storage layers are disposed over a top surface of the fin structure and the gate dielectric layers are disposed on sidewalls of the fin structure. n=2 x , x is a whole number greater or equal to 1. A transistor can interchange between a select transistor and a storage transistor.
1 . A device comprising:
a substrate; and
a fin structure disposed on the substrate, the fin structure serves as a common body of n transistors, the transistors comprise separate charge storage layers and gate dielectric layers, the charge storage layers disposed over a top surface of the fin structure and the gate dielectric layers disposed on sidewalls of the fin structure, wherein n=2 x , x is a whole number greater or equal to 1, wherein a transistor can interchange between a select transistor and a storage transistor.
2 . The device in claim 1 wherein the device is a multi-bit memory cell with n number of bits.
3 . The device in claim 1 wherein the transistor comprises n number of gates, a gate can interchange between a select gate and a control gate.
4 . The device in claim 3 wherein the gate comprises a gate electrode which wraps around the fin structure.
5 . The device in claim 3 wherein the gate comprises first and second sub-gates which are separated by sidewalls of the fin structure.
6 . The device in claim 3 comprises doped regions in the fin structure adjacent to the gate.
7 . The device in claim 1 wherein the charge storage layers comprise an oxide-nitride-oxide stack.
8 . A method of forming a device comprising:
providing a substrate; and
forming a fin structure disposed on the substrate, the fin structure serves as a common body of n transistors, the transistors comprise separate charge storage layers and gate dielectric layers, the charge storage layers disposed over a top surface of the fin structure and the gate dielectric layers disposed on sidewalls of the fin structure, wherein n=2 x , x is a whole number greater or equal to 1, wherein a transistor can interchange between a select transistor and a storage transistor.
9 . The method in claim 8 wherein the device is a multi-bit memory cell with n number of bits.
10 . The method in claim 8 wherein the transistor comprises n number of gates, a gate can interchange between a select gate and a control gate.
11 . The method in claim 10 wherein the gate comprises a gate electrode which wraps around the fin structure.
12 . The method in claim 10 wherein the gate comprises first and second sub-gates which are separated by sidewalls of the fin structure.
13 . The method in claim 8 comprises forming protection layers on sidewalls of the charge storage layers.
14 . The method in claim 13 wherein the charge storage layers comprise an oxide-nitride-oxide stack.
15 . The method in claim 8 comprises forming doped regions in the fin structure adjacent to the gate.
16 . The method in claim 15 wherein the doped regions comprises source/drain regions which are coupled to a select line and a bitline.
17 . A multi-bit device comprising:
a substrate;
a fin structure disposed on the substrate, the fin structure serves as a common body of n transistors which are coupled in series between first and second cell terminals, the transistors comprise separate charge storage layers and gate dielectric layers, the charge storage layers disposed over a top surface of the fin structure and the gate dielectric layers disposed on sidewalls of the fin structure, wherein n=2 x , x is a whole number greater or equal to 1, wherein a transistor can interchange between a select transistor and a storage transistor;
wherein a transistor comprises first and second source/drain terminals, first source/drain terminal of the first transistor is coupled to the first cell terminal, second source/drain terminal of the last transistor is coupled to the second cell terminal, second source/drain terminal and first source/drain terminal of adjacent transistors form a common source/drain region in the fin structure.
18 . The multi-bit device in claim 17 wherein a transistor comprises n number of gates, a gate can interchange between a select gate and a control gate.
19 . The multi-bit device in claim 18 wherein the transistor comprises a gate electrode which wraps around the fin structure.
20 . The multi-bit device in claim 18 wherein the gate comprises first and second sub-gates which are separated by sidewalls of the fin structure.