ESD-robust I/O driver circuits

1. A circuit comprising:

a first NMOS transistor having a first source, a first drain, and a first gate, wherein the first source is coupled to a ground rail, and the first drain is coupled to an I/O pad;

a gate driver control circuit including a second NMOS transistor having a second source, a second drain, and a second gate, wherein the second drain is coupled to the first gate, the second source is coupled to the ground rail, and the gate driver control circuit provides a ground potential to the first gate during an ESD event occurring from the I/O pad to the ground rail; and

an ESD clamp including a third NMOS transistor having a third source, a third drain, and a third gate, wherein the second and third gates are coupled.

2. The circuit according to claim 1 , wherein the ESD clamp controls a switch to turn on the second NMOS transistor during the ESD event, and turns off the second NMOS transistor during normal operation.

3. The circuit according to claim 1 , wherein the ESD clamp provides a turn-on signal to the second gate during the ESD event.

4. The circuit according to claim 2 , wherein the ESD clamp further includes:

an inverter having an output terminal coupled to the second and third gates, wherein the output terminal provides a turn-on signal to the second and third gates during the ESD event.

5. The circuit according to claim 4 , wherein the output terminal provides a turn-off signal to the second and third gates during normal operation.

6. The circuit according to claim 4 , wherein ESD current flows from the I/O pad to the ground rail through the third NMOS transistor during the ESD event.

7. The circuit according to claim 4 , further comprising:

a PMOS transistor having a fourth source, a fourth drain, and a fourth gate, wherein the fourth drain is coupled to the first drain, and the fourth source is coupled to the third drain.

8. The circuit according to claim 7 , further comprising:

an ESD device coupled to the I/O pad and the first drain, wherein ESD current flows from the I/O pad to the ground rail through the ESD device during the ESD event.

9. The circuit according to claim 8 , wherein the ESD device includes a fourth NMOS transistor having a fifth source, a fifth drain, and a fifth gate, and wherein the fifth source and the fifth gate is coupled to the ground rail, and the fifth drain is coupled to the I/O pad.

10. A method comprising:

providing a first NMOS transistor having a first source, a first drain, and a first gate;

coupling the first source to a ground rail, and the first drain to an I/O pad;

providing a gate driver control circuit including a second NMOS transistor having a second source, a second drain, and a second gate;

coupling the second drain to the first gate, the second source to the ground rail, wherein the gate driver control circuit provides a ground potential to the first gate during an ESD event occurring from the I/O pad to the ground rail; and

providing an ESD clam including a third NMOS transistor having a third source a third drain, and a third gate, wherein the second and third gates are coupled.

11. The method according to claim 10 , wherein the ESD clamp controls a switch to turn on the second NMOS transistor during the ESD event, and turns off the second NMOS transistor during normal operation.

12. The method according to claim 10 ,

wherein the ESD clamp provides a turn-on signal to the second gate during the ESD event.

13. The method according claim 11 , further comprising:

providing the ESD clamp with an inverter having an output terminal; and

coupling the output terminal to the second and third gates, wherein the output terminal provides a turn-on signal to the second and third gates during the ESD event.

14. The method according to claim 13 , wherein the output terminal provides a turn-off signal to the second and third gates during normal operation.

15. The method according to claim 13 , wherein ESD current flows from the I/O pad to the ground rail through the third NMOS transistor during the ESD event.

16. The method according to claim 13 , further comprising:

providing a PMOS transistor having a fourth source, a fourth drain, and a fourth gate; and

coupling the fourth drain to the first drain, and the fourth source to the third drain.

17. The method according to claim 16 , further comprising:

providing an ESD device; and

coupling the ESD device to the I/O pad and the first drain, wherein ESD current flows from the I/O pad to the ground rail through the ESD device during the ESD event.

18. The method according to claim 17 , further comprising:

providing the ESD device with a fourth NMOS transistor having a fifth source, a fifth drain, and a fifth gate; and

coupling the fifth source and the fifth gate to the ground rail, and the fifth drain to the I/O pad.

19. A ring I/O circuit having a plurality of I/O cells, each of the I/O cells comprising:

an I/O pad;

a first NMOS transistor having a first source, a first drain, and a first gate, wherein the first source is coupled to a ground rail, and the first drain is coupled to the I/O pad;

a gate driver control circuit including a second NMOS transistor having a second source, a second drain, and a second gate, wherein the second drain is coupled to the first gate, the second source is coupled to the ground rail, and the gate driver control circuit provides a ground potential to the first gate during an ESD event occurring from the I/O pad to the ground rail; and

an ESD clamp including a third NMOS transistor having a third source, a third drain, and a third gate, wherein the second and third gates are coupled.

20. The ring I/O circuit according to claim 19 , wherein the ESD clamp further comprises:

an inverter having an output terminal coupled to at least some of the second and third gates, wherein the output terminal provides a turn-on signal to the coupled second and third gates during the ESD event, and a turn-off signal to the coupled second and third gates during normal operation.