P-channel multi-time programmable (MTP) memory cells

1. A multi-time programmable (MTP) memory cell comprising:

a semiconductor substrate;

an isolation region formed in the semiconductor substrate and extending to a first depth;

an n-well formed in the semiconductor substrate and extending to a second depth greater than the first depth;

a p-channel transistor disposed over the n-well and including a transistor gate;

a p-well formed in the semiconductor substrate and extending to a third depth greater than the first depth, wherein the p-well contacts the isolation region at the first depth and is isolated from the n-well by the isolation region; and

a p-channel capacitor disposed over the p-well and including a capacitor gate, wherein the capacitor gate is coupled to the transistor gate.

2. The MTP memory cell of claim 1 wherein the second depth is equal to the third depth.

3. The MTP memory cell of claim further comprising a p-doped deep well formed in the semiconductor substrate, wherein the n-well lies above and directly in contact with the p-doped deep well, and wherein the p-well lies above and directly in contact with the p-doped deep well.

4. The MTP memory cell of claim 1 further comprising a p-doped deep well formed in the semiconductor substrate, wherein the n-well lies above the p-doped deep well, and wherein the p-well lies above the p-doped deep well.

5. The MTP memory cell of claim 1 further comprising:

an n-doped deep well formed in the semiconductor substrate; and

a p-doped deep well formed in the semiconductor substrate and lying over the n-doped deep well, wherein the n-well lies over the p-doped deep well, and wherein the p-well lies over the p-doped deep well.

6. The MTP memory cell of claim 1 further comprising:

a p-doped deep well formed in the semiconductor substrate; and

a native undoped region of the semiconductor substrate located between the isolation region and the p-doped deep well.

7. The MTP memory cell of claim 1 wherein the n-well is isolated from the p-well by a native undoped region of the semiconductor substrate and the isolation region overlying the native undoped region.

8. The MTP memory cell of claim 1 further comprising an erase terminal coupled to the transistor gate.

9. The MTP memory cell of claim 8 wherein the erase terminal comprises an n-channel transistor.

10. The MTP memory cell of claim 9 wherein the n-channel transistor is formed over the p-well.

11. The MTP memory cell of claim 10 wherein the n-channel transistor includes a first n-doped diffusion region, a second n-doped diffusion region, and an n-channel transistor gate between the first n-doped diffusion region and the second n-doped diffusion region.

12. The MTP memory cell of claim 11 wherein the second n-doped diffusion region is coupled to an erase gate line.

13. The MTP memory cell of claim 11 wherein the n-channel transistor includes a lightly doped drain region, and wherein the second n-doped diffusion region is separated from the n-channel transistor gate by the lightly doped drain region.

14. The MTP memory cell of claim 1 wherein the isolation region extends from an upper surface to the first depth, and wherein the p-well contacts the isolation region continuously from the upper surface to the first depth.

15. A multi-time programmable (MTP) memory cell comprising:

a semiconductor substrate;

a p-doped deep well formed in the semiconductor substrate;

a shallow isolation region formed in the semiconductor substrate;

a native undoped region of the semiconductor substrate located between the shallow isolation region and the p-doped deep well;

an n-well formed in the semiconductor substrate;

a p-channel transistor disposed over the n-well and including a transistor gate;

a p-well formed in the semiconductor substrate and isolated from the n-well by the native undoped region of the semiconductor substrate and the shallow isolation region; and

a p-channel capacitor disposed over the p-well and including a capacitor gate, wherein the capacitor gate is coupled to the transistor gate.

16. A multi-time programmable (MTP) memory cell comprising:

a semiconductor substrate;

an n-well formed in the semiconductor substrate;

a p-channel transistor disposed over the n-well and including a transistor gate;

a p-well formed in the semiconductor substrate and isolated from the n-well;

a p-channel capacitor disposed over the p-well and including a capacitor gate, wherein the capacitor gate is coupled to the transistor gate; and

an erase terminal formed over the p-well and coupled to the transistor gate.

17. The MTP memory cell of claim 16 wherein the erase terminal comprises an n-channel transistor.

18. The MTP memory cell of claim 16 wherein the erase terminal comprises an n-channel transistor, and wherein the n-channel transistor includes a first n-doped diffusion region, a second n-doped diffusion region, and an n-channel transistor gate between the first n-doped diffusion region and the second n-doped diffusion region.

19. The MTP memory cell of claim 16 wherein the erase terminal comprises an n-channel transistor; wherein the n-channel transistor includes a first n-doped diffusion region, a second n-doped diffusion region, and an n-channel transistor gate between the first n-doped diffusion region and the second n-doped diffusion region; and

wherein the second n-doped diffusion region is coupled to an erase gate line.

20. The MTP memory cell of claim 16 wherein the erase terminal comprises an n-channel transistor; wherein the n-channel transistor includes a first n-doped diffusion region, a second n-doped diffusion region, and an n-channel transistor gate between the first n-doped diffusion region and the second n-doped diffusion region; wherein the n-channel transistor includes a lightly doped drain region; and wherein the second n-doped diffusion region is separated from the n-channel transistor gate by the lightly doped drain region.