Dielectric posts in metal layers
View Patent ↗A semiconductor device is disclosed. The semiconductor device includes a substrate comprises a plurality of metal layers. The semiconductor device also includes dielectric posts disposed in the metal layers. The density of the dielectric posts in the metal layers is equal to about 15-25%.
1. A semiconductor device comprising:
a substrate comprises a plurality of metal layers; and
dielectric posts disposed in the metal layers, wherein the metal layers comprise wide metal lines, the dielectric posts extend the thickness of the wide metal lines and the density of the dielectric posts in the metal layers is equal to about 15-25%.
2. The semiconductor device of claim 1 further comprising via bar disposed in between adjacent metal layers.
3. The semiconductor device of claim 2 wherein the metal layers are disposed in a crack stop region.
4. The semiconductor device of claim 3 wherein the via bar comprises a mesh design or a straight line design.
5. The semiconductor device of claim 4 wherein the mesh design comprises a series of intersecting first lines in a first direction along a width of the metal line and second lines in a second direction along a length of the metal line and the intersections of the first and second lines form a plurality of cells.
6. The semiconductor device of claim 1 wherein the wide metal lines are about 4.5-7 μm wide.
7. The semiconductor device of claim 1 wherein the wide metal lines are wider than about 7 μm wide.
8. The semiconductor device of claim 1 wherein the dielectric posts comprise a dielectric material.
9. The semiconductor device of claim 5 wherein at least one of the dielectric posts is disposed within lines of a cell of the via bar.
10. The semiconductor device of claim 4 wherein the dielectric posts do not come into contact with the via bars above and below the wide metal lines.
11. A semiconductor device comprising:
a substrate comprises a plurality of metal levels having metal layers disposed in a crack stop region; and
dielectric posts disposed in the metal layers, wherein the metal layers comprise wide metal lines, the dielectric posts extend the thickness of the wide metal lines and the density of the dielectric posts in the metal layers is equal to about 15-25%.
12. The semiconductor device of claim 11 further comprising via levels disposed in between adjacent metal levels.
13. The semiconductor device of claim 12 wherein via bars are disposed in the via levels.
14. The semiconductor device of claim 13 wherein the via bars comprise a mesh design or straight line design.
15. The semiconductor device of claim 14 wherein the mesh design comprises a series of intersecting first lines in a first direction along a width of the metal line and second lines in a second direction along a length of the metal line and the intersections of the first and second lines form a plurality of cells.
16. The semiconductor device of claim 11 wherein the wide metal lines are about 4.5-7 μm wide.
17. The semiconductor device of claim 11 wherein the dielectric posts comprise a dielectric material.
18. The semiconductor device of claim 15 wherein at least one of the dielectric posts is disposed within lines of a cell of the via bar.
19. The semiconductor device of claim 14 wherein the dielectric posts do not come into contact with the via bars above and below the wide metal lines.
20. A semiconductor device comprising:
a substrate prepared with circuit components formed thereon, the substrate having a crack-stop region disposed in a peripheral region of the circuit components;
a plurality of metal layers disposed in the crack-stop region; and
dielectric posts disposed in the metal layers, wherein the metal layers comprise wide metal lines, the dielectric posts extend the thickness of the wide metal lines and the density of the dielectric posts in the metal layers is equal to about 15-25%.