Methods for producing integrated circuits with interposers and integrated circuits produced from such methods

1. A method of producing an integrated circuit comprising:

producing an interposer comprising an insulation plate and a plurality of through vias passing through the insulation plate, wherein the interposer comprises a prime area and a frame area; and

forming a prime area test circuit in a chip location of the prime area, wherein the prime area test circuit comprises a portion of the plurality of through vias that are electrically connected in series, wherein the portion of the plurality of through vias of the prime area test circuit are electrically isolated from an integrated circuit chip, and wherein; and

electrically connecting the integrated circuit chip to the chip location of the interposer, wherein the chip location directly underlies the integrated circuit chip, wherein the prime area is defined by the geography of the interposer that includes through vias that electrically connect the integrated circuit chip to another component of the integrated circuit, and the frame area is defined by the geography of the interposer outside of the prime area that includes through vias that are electrically isolated from the integrated circuit chip, and wherein the frame area does not include through vias that are electrically connected to the integrated circuit chip.

2. The method of claim 1 further comprising:

forming a top redistribution layer on a top side of the interposer, wherein the top redistribution layer electrically connects the prime area test circuit to a test pad on the top side.

3. The method of claim 2 further comprising:

electrically interrogating the prime area test circuit; and

covering the test pad with an overmold after electrically interrogating the prime area test circuit, wherein the overmold comprises an electrically insulating material.

4. The method of claim 1 wherein:

forming the prime area test circuit comprises forming the prime area test circuit such that at least a portion of the prime area test circuit is in a position other than the chip location.

5. The method of claim 4 wherein:

forming the prime area test circuit comprises forming the prime area test circuit in a border area of the prime area, wherein the border area is different than the chip location that directly underlies the integrated circuit chip.

6. The method of claim 1 further comprising:

forming a bottom redistribution layer underlying a bottom side of the insulation plate; and

forming an interposer ball underlying the bottom redistribution layer, wherein the bottom redistribution layer electrically connects the prime area test circuit to the interposer ball.

7. The method of claim 1 wherein forming the prime area test circuit further comprises forming a plurality of prime area test circuits in the prime area.

8. A method of producing an integrated circuit comprising:

forming a prime area test circuit in an interposer, wherein the interposer comprises an insulation plate and a plurality of through vias passing through the insulation plate, and wherein the prime area test circuit comprises a portion of the plurality of through vias that are within the prime area, and wherein at least a portion of the prime area test circuit is in a chip location;

electrically interrogating the prime area test circuit;

connecting an integrated circuit chip to the interposer after electrically interrogating the prime area test circuit, wherein the integrated circuit chip is positioned within the prime area, wherein the chip location directly underlies the integrated circuit chip, and wherein the prime area is defined by the geography of the interposer that includes through vias that electrically connect the integrated circuit chip to another component of the integrated circuit; and

wherein forming the prime area test circuit comprises forming the prime area test circuit such that the portion of the plurality of through vias of the prime area test circuit is electrically isolated from the integrated circuit chip.

9. The method of claim 8 wherein:

forming the prime area test circuit comprises forming at least a portion of the prime area test circuit in an area other than the chip location.

10. The method of claim 9 wherein forming the prime area test circuit comprises:

forming at least a portion of the prime area test circuit in a border area of the prime area, wherein the border area is different than the chip location.

11. The method of claim 8 further comprising:

forming the prime area test circuit further comprises forming a test pad in electrical communication with the portion of the plurality of the through vias of the prime area test circuit.

12. The method of claim 11 wherein:

electrically interrogating the prime area test circuit comprises electrically contacting the test pad with an electrical probe of a test device.

13. The method of claim 11 further comprising covering the integrated circuit chip and the test pad with an overmold.

14. The method of claim 8 wherein forming the prime area test circuit comprises:

electrically connecting the portion of the plurality of through vias of the prime area test circuit in series.

15. The method of claim 8 further comprising: forming a frame area test circuit in a frame area, wherein the frame area is defined by the geography of the interposer outside of the prime area that includes through vias that are electrically isolated from the integrated circuit chip, and wherein the frame area does not include through vias that are electrically connected to the integrated circuit chip.

16. The method of claim 8 wherein electrically interrogating the prime area test circuit comprises electrically interrogating a plurality of prime area test circuits.