Integrated circuit system employing sacrificial spacers
View Patent ↗An integrated circuit system that includes: providing a substrate including a first device and a second device; configuring the first device and the second device to include a first spacer, a first liner made from a first dielectric layer, and a second spacer made from a sacrificial spacer material; forming a second dielectric layer over the integrated circuit system; forming a first device source/drain and a second device source/drain adjacent the second spacer and through the second dielectric layer; removing the second spacer without damaging the substrate; forming a third dielectric layer over the integrated circuit system before annealing; and forming a fourth dielectric layer over the integrated circuit system that promotes stress within the channel of the first device, the second device, or a combination thereof.
1. An integrated circuit system comprising:
providing a substrate including a first device and a second device;
configuring the first device and the second device to include a first spacer, a first liner made from a first dielectric layer, and a second spacer made from a sacrificial spacer material;
forming a second dielectric layer over the integrated circuit system;
forming a first device source/drain and a second device source/drain adjacent the second spacer and through the second dielectric layer;
removing the second spacer without damaging the substrate;
forming a third dielectric layer over the integrated circuit system before annealing; and
forming a fourth dielectric layer over the integrated circuit system that promotes stress within the channel of the first device, the second device, or a combination thereof.
2. The system as claimed in claim 1 wherein:
configuring the first device and the second device to include the second spacer made from a sacrificial spacer material includes the second spacer made from amorphous carbon or a thermally decomposable material.
3. The system as claimed in claim 1 wherein:
removing the second spacer without damaging the substrate includes an ashing etch process or a thermal etch process.
4. The system as claimed in claim 1 wherein:
forming the second dielectric layer protects the second spacer.
5. The system as claimed in claim 1 wherein:
forming the fourth dielectric layer includes forming a tensile or compressive stress inducing layer.
6. An integrated circuit system comprising:
providing a substrate including a first device;
configuring the first device to include a first spacer, a first liner and a second spacer made from a thermally decomposable material;
forming a first device source/drain;
removing the second spacer; and
forming an electrical contact adjacent the first liner.
7. The system as claimed in claim 6 wherein:
providing the first device includes providing a PFET device or an NFET device.
8. The system as claimed in claim 6 wherein:
removing the second spacer includes removing the second spacer by a thermal etch process.
9. The system as claimed in claim 6 wherein:
removing the second spacer prevents silicide piping from the electrical contact.
10. The system as claimed in claim 6 wherein:
removing the second spacer allows a stress inducing layer to be placed adjacent a channel of the first device.
11. An integrated circuit system comprising:
providing a substrate including a first device and a second device;
configuring the first device and the second device to include a first spacer, a first liner and a second spacer made from a thermally decomposable material;
forming a first device source/drain and a second device source/drain;
removing the second spacer; and
forming an electrical contact adjacent the first liner of the first device and the second device.
12. The system as claimed in claim 11 wherein:
configuring the first device and the second device to include the second spacer made from the thermally decomposable material includes the second spacer made from a hydrocarbon-siloxane polymer hyrbrid.
13. The system as claimed in claim 11 wherein:
removing the second spacer includes removing the second spacer via a thermal etch process that does not damage the substrate.
14. The system as claimed in claim 11 further comprising:
forming a second dielectric layer to protect the second spacer.
15. The system as claimed in claim 11 further comprising:
forming a stress inducing layer over the integrated circuit system that promotes stress within the channel of the first device, the second device, or a combination thereof.
16. The system as claimed in claim 11 wherein:
removing the second spacer prevents silicide piping from the electrical contact.
17. The system as claimed in claim 11 wherein:
providing the first device includes providing a PFET device and providing the second device includes providing an NFET device.
18. The system as claimed in claim 11 wherein:
removing the second spacer allows a stress inducing layer to be placed adjacent a channel of the first device, the second device, or a combination thereof.
19. The system as claimed in claim 11 further comprising:
forming a third dielectric layer over the integrated circuit system to prevent out-diffusion of dopants during annealing.
20. The system as claimed in claim 11 further comprising:
forming a source/drain extension and a halo region for each of the first device and the second device.