FinFET with novel body contact for multiple Vt applications
View Patent ↗FinFET devices are formed with body contact structures enabling the fabrication of such devices having different gate threshold voltages (Vt). A body contact layer is formed to contact the gate electrode (contact) enabling a forward body bias and a reduction in Vt. Two example methods of fabrication (and resulting structures) are provided. In one method, the gate electrode (silicon-based) and body contact layer (silicon) are connected by growing epitaxy which merges the two structures forming electrical contact. In another method, a via is formed that intersects with the gate electrode (suitable conductive material) and body contact layer and is filled with conductive material to electrically connect the two structures. As a result, various FinFETs with different Vt can be fabricated for different applications.
1. A Fin field-effect transistor (FinFET) device comprising:
a substrate formed of insulating material;
a fin structure disposed above the substrate;
a body layer comprising silicon, the body layer including a first portion disposed underneath at least a portion of the fin structure and including a body contact layer portion having dopants of a first conductivity type;
a gate stack including a gate dielectric and a gate electrode, wherein the gate electrode comprises silicon, the gate stack formed at least partially around the fin structure and disposed above the body contact layer portion;
a dielectric material overlying the body contact layer portion and the gate stack;
a via formed through the dielectric material for exposing at least portions of the body contact layer portion and the gate electrode;
first conductive material disposed within the via for electrically coupling the body contact layer portion and the gate electrode; and
wherein the via is wider than a width of the gate stack and a portion of the first conductive material is disposed beneath the body contact layer portion.
2. The FinFET device in accordance with claim 1 wherein the gate electrode comprises conductive material.
3. The FinFET device in accordance with claim 1 wherein the fin structure comprises:
a channel portion having dopants of the first conductivity type;
a first source/drain (S/D) region having dopants of a second conductivity type; and
a second S/D region having dopants of the second conductivity type.
4. A method of fabricating a Fin field-effect transistor (Fin FET), the method comprising:
providing an insulating substrate;
forming a fin structure above the substrate;
forming a body layer comprising silicon, the body layer including a first portion disposed underneath at least a portion of the fin structure and including a body contact layer portion of a first conductivity type;
forming a gate stack including a gate dielectric and a gate electrode, wherein the gate electrode comprises silicon, the gate stack positioned at least partially around the fin structure and disposed above the body contact layer portion;
forming a dielectric material overlying the body contact layer portion and the gate stack;
forming a via through the dielectric material for exposing at least portions of the body contact layer portion and the gate electrode;
disposing first conductive material within the via for electrically coupling the body contact layer portion and the gate electrode; and
wherein the via is formed wider than a width of the gate stack and a portion of the first conductive material is disposed beneath the body contact layer portion.
5. The method in accordance with claim 4 wherein forming the via further comprises:
etching using an acid dip.