Reliable contacts
View Patent ↗A method for forming a device is disclosed. The method includes providing a substrate prepared with first and second contact regions and a dielectric layer over the contact region. First and second vias are formed in the dielectric layer. The first via is in communication with the first contact region and the second via is in communication with the second contact region. A buried void provides a communication path between the first and second vias. The vias and buried void are at least partially filled with a dielectric filler. The partially filled buried void blocks the communication path between the first and second vias created by the buried void. The dielectric filler in the vias is removed, leaving remaining dielectric filler in the buried void to block the communication path between the first and second vias and contact plugs are formed in the vias.
1. A device comprising:
a substrate having first and second contact regions and a dielectric layer over the contact regions;
first and second transistors over the substrate, wherein each of the transistors includes a gate conductor with first and second source/drain (S/D) regions;
an etch stop layer disposed over the transistors;
first and second vias in the dielectric layer, the first via is in communication with the first contact region and the second via is in communication with the second contact region, and a buried void which provides a communication path between the first and second vias, wherein the buried void is within the etch stop layer and extends to at least a portion of the dielectric layer, the buried void is at least partially filled with a dielectric filler, the partially filled buried void blocks the communication path between the first and second vias created by the buried void; and
contact plugs, wherein the contact plugs are disposed in the vias.
2. The device of claim 1 wherein the first and second transistors share a common S/D region.
3. The device of claim 1 wherein the buried void is located between adjacent gate conductors of the transistors.
4. The device of claim 3 wherein the buried void extends across the length of the gate conductors.
5. The device of claim 1 wherein the buried void is completely filled with the dielectric filler.
6. The device of claim 1 wherein the dielectric filler comprises a material which can be selectively etched with respect to the dielectric layer.
7. The device of claim 6 wherein the dielectric filler comprises a flowable dielectric material.
8. The device of claim 1 wherein the contact plugs contact the source/drain regions.
9. A device comprising:
a substrate having first and second contact regions and a dielectric layer over the contact regions;
first and second transistors over the substrate, wherein each of the transistors includes a gate conductor with first and second source/drain (S/D) regions;
an etch stop layer disposed over the transistors;
first and second vias in the dielectric layer, the first via is in communication with the first contact region and the second via is in communication with the second contact region, and a buried void which provides a communication path between the first and second vias, wherein the buried void is within the etch stop layer and extends to at least a portion of the dielectric layer, the buried void is at least partially filled with a dielectric filler which comprises a polymer, the partially filled buried void blocks the communication path between the first and second vias created by the buried void; and
contact plugs, wherein the contact plugs are disposed in the vias.
10. The device of claim 9 wherein the buried void is located between adjacent gate conductors of the transistors.
11. The device of claim 10 wherein the buried void extends across the length of the gate conductors.
12. The device of claim 9 wherein the buried void is completely filled with the dielectric filler.
13. The device of claim 9 wherein the contact plugs contact the source/drain regions.
14. A device comprising:
a substrate having first and second contact regions and a dielectric layer over the contact regions;
first and second transistors over the substrate, wherein each of the transistors includes a gate conductor with first and second source/drain (S/D) regions;
an etch stop layer disposed over the transistors;
first and second vias extend from a top of the dielectric layer towards at least a portion of the etch stop layer, and a buried void which provides a communication path between the first and second vias, wherein the buried void is within the etch stop layer and extends to at least a portion of the dielectric layer, the buried void is at least partially filled with a dielectric filler, the partially filled buried void blocks the communication path between the first and second vias created by the buried void; and
contact plugs, wherein the contact plugs are disposed in the vias.
15. The device of claim 14 wherein the buried void is completely filled with the dielectric filler.