Integrated circuits with FinFET nonvolatile memory
Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a first and second fin overlying a substrate, where the first and second fins intersect at a fin intersection. The first fin has a first fin left end. A tunnel dielectric and a floating gate are formed adjacent to the first fin with the tunnel dielectric between the floating gate and the first fin. An interpoly dielectric is formed adjacent to the floating gate, and a control gate is formed adjacent to the interpoly dielectric such that the interpoly dielectric is between the floating gate and the control gate. The control gate, interpoly dielectric, floating gate, and the tunnel dielectric are removed from over the first fin except for at a floating gate position between the first fin left end and the fin intersection.
1. A method of producing an integrated circuit comprising:
forming a first fin overlying a substrate, wherein the first fin extends in a first direction, and wherein the first fin comprises a first fin left end;
forming a second fin overlying the substrate, wherein the second fin extends in a second direction different than the first direction, and wherein the second fin intersects the first fin at a fin intersection;
forming a tunnel dielectric adjacent to the first fin;
forming a floating gate adjacent to the first fin such that the tunnel dielectric is positioned between the floating gate and the first fin;
forming an interpoly dielectric adjacent to the floating gate;
forming a control gate adjacent to the interpoly dielectric such that the interpoly dielectric is positioned between the floating gate and the control gate; and
removing the control gate, the interpoly dielectric, the floating gate, and the tunnel dielectric from over the first fin except for at a floating gate position, wherein the floating gate position is between the first fin left end and the fin intersection.
2. The method of claim 1 further comprising:
forming a select gate overlying the first fin at a select gate position, wherein the select gate position is adjacent to the floating gate position.
3. The method of claim 2 wherein:
forming the floating gate adjacent to the first fin comprises forming a plurality of floating gates adjacent to the first fin at a plurality of floating gate positions, wherein the plurality of floating gate positions comprise the floating gate position between a first fin right end and the fin intersection; and
forming the select gate adjacent to the first fin comprises forming a plurality of select gates adjacent to the first fin at a plurality of select gate positions, wherein the plurality of select gate positions comprise the select gate position between the first fin right end and the fin intersection.
4. The method of claim 2 further comprising:
forming a select gate dielectric overlying the first fin at the select gate position, wherein the select gate dielectric is positioned between the select gate and the first fin, the select gate dielectric is positioned between the floating gate and the select gate, and the select gate dielectric is positioned between the control gate and the select gate.
5. The method of claim 2 further comprising:
forming a spacer overlying the first fin and adjacent to the select gate position, wherein the spacer is positioned between the select gate and the first fin left end.
6. The method of claim 1 further comprising:
forming an erase gate dielectric overlying the second fin; and
forming an erase gate overlying the erase gate dielectric.
7. The method of claim 1 wherein forming the first fin comprises etching the first fin into a buried oxide underlying the substrate, wherein the buried oxide overlies a carrier, the method further comprising:
providing a ground plane dielectric underlying the first fin, wherein the ground plane dielectric overlies the carrier; and
forming a contact to the carrier.
8. The method of claim 1 wherein forming the interpoly dielectric comprises forming a first oxide layer, a nitride layer, and a second oxide layer, and wherein the nitride layer is positioned between the first oxide layer and the second oxide layer.
9. The method of claim 1 wherein forming the second fin comprises forming the second fin such that the fin intersection is at a first fin right end.
10. A method of producing an integrated circuit comprising:
forming a first fin overlying a substrate, wherein the first fin extends in a first direction and wherein the first fin comprises a first fin left end;
forming a drain on the first fin left end;
forming a second fin overlying the substrate, wherein the second fin extends in a second direction different than the first direction, and wherein the second fin intersects the first fin at a fin intersection;
forming a floating gate adjacent to the first fin at a floating gate position between the first fin left end and the fin intersection;
forming a control gate overlying the floating gate and the first fin; and
forming a select gate overlying the first fin at a select gate position, wherein the select gate position is between the first fin left end and the fin intersection, and wherein the select gate position is adjacent to the floating gate position.
11. The method of claim 10 further comprising:
forming an erase gate dielectric overlying the second fin, wherein the erase gate dielectric is adjacent to the floating gate and the control gate; and
forming an erase gate overlying the erase gate dielectric such that the erase gate dielectric is positioned between the erase gate and the floating gate, and the erase gate dielectric is positioned between the erase gate and the control gate.
12. The method of claim 10 wherein forming the first fin comprise etching the substrate and a buried oxide underlying the substrate to form the first fin, wherein a carrier is positioned underlying the buried oxide, the method further comprising:
providing a ground plane dielectric overlying the carrier; and
forming a ground plane contact to the substrate.
13. The method of claim 10 further comprising:
forming a tunnel dielectric between the floating gate and the first fin.
14. The method of claim 10 further comprising:
forming an interpoly dielectric between the floating gate and the control gate.
15. The method of claim 14 wherein forming the interpoly dielectric comprises forming a first oxide layer, a nitride layer, and a second oxide layer, and wherein the nitride layer is positioned between the first oxide layer and the second oxide layer.
16. The method of claim 10 further comprising:
forming a select gate dielectric between the first fin and the select gate, wherein the select gate dielectric is also positioned between the select gate and the floating gate and the select gate dielectric is positioned between the select gate and the control gate.
17. The method of claim 10 wherein:
forming the floating gate adjacent to the first fin comprises forming a plurality of floating gates adjacent to the first fin at a plurality of floating gate positions, wherein the plurality of floating gate positions comprise the floating gate position between a first fin right end and the fin intersection; and
forming the select gate adjacent to the first fin comprises forming a plurality of select gates adjacent to the first fin at a plurality of select gate positions, wherein the plurality of select gate positions comprise the select gate position between the first fin right end and the fin intersection.
18. The method of claim 17 wherein forming the second fin comprises forming the second fin such that the fin intersection is at the first fin right end.
19. The method of claim 10 further comprising:
forming a spacer adjacent to the select gate such that the spacer is positioned between the select gate and the first fin left end, and wherein the spacer overlies the first fin.