Method and apparatus for embedded NVM utilizing an RMG process
View Patent ↗A memory device is fabricated through the integration of embedded non-volatile memory (eNVM) with RMG processes. Embodiments include forming a first and a second dual polysilicon gate-stack structure on an upper surface of a substrate, forming spacers on opposite sidewalls of each of the first and the second dual polysilicon gate-stack structures, forming an ILD adjacent to an exposed sidewall of each spacer, removing the first dual polysilicon gate-stack structure, forming a first cavity between the spacers, and forming a HKMG in the first cavity, wherein the HKMG forms an access gate.
1. A method comprising:
forming a first dual polysilicon gate-stack structure and a second dual polysilicon gate-stack structure on an upper surface of a substrate;
forming spacers on opposite sidewalls of the first dual polysilicon gate-stack structure and the second dual polysilicon gate-stack structure;
forming an inter-layer dielectric (ILD) adjacent to an exposed sidewall of the spacers;
removing the first dual polysilicon gate-stack structure, forming a first cavity between the spacers; and
forming a high-k/metal gate (HKMG) in the first cavity, wherein the HKMG comprises an access gate.
2. The method according to claim 1 , further comprising forming the first dual polysilicon gate-stack structure and the second dual polysilicon gate-stack structure by:
forming a floating gate layer on a tunnel-oxide layer, on the upper surface of the substrate;
forming a blocking oxide layer on the floating gate layer;
forming a control gate layer on the blocking oxide layer; and
etching the floating gate, the blocking oxide, and the control gate layers.
3. The method according to claim 1 , further comprising:
forming source/drain regions in the substrate for the first dual polysilicon gate-stack structure and the second dual polysilicon gate-stack structure prior to forming the ILD.
4. The method according to claim 3 , further comprising:
forming a hard-mask layer over the HKMG and the second dual polysilicon gate-stack structure; and
forming contacts on the source/drain regions through the ILD.
5. The method according to claim 3 , further comprising:
forming a silicide on the source/drain regions prior to forming the ILD;
forming a hard-mask layer over the HKMG and the second dual polysilicon gate-stack structure; and
forming contacts on the silicide.
6. A method comprising:
forming a first gate-stack structure on an upper surface of a substrate, the first gate-stack structure comprising a first floating gate layer, a first blocking oxide layer on the first floating gate layer, and a first hard-mask layer on the first blocking oxide layer;
forming a second gate-stack structure on the upper surface of the substrate, the second gate stack structure comprising a second floating gate layer, a second blocking oxide layer on the second floating gate layer, and a second hard-mask layer on the second blocking oxide layer;
forming first spacers on opposite sidewalls of the first gate-stack structure and second spacers on opposite sidewalls of the second gate-stack structure;
forming an inter-layer dielectric (ILD) adjacent to an exposed sidewall of the first spacers and the second spacers;
removing the first hard-mask layer, the first blocking oxide layer, and the first floating gate layer, forming a first cavity between the first spacers; and
forming a first high-k/metal gate (HKMG) in the first cavity.
7. The method according to claim 6 , further comprising:
removing the second hard-mask layer substantially simultaneously with removal of the first hard-mask layer, forming a second cavity between the second spacers; and
forming a second HKMG in the second cavity substantially simultaneously with forming the first HKMG in the first cavity, wherein the first HKMG comprises an access gate and the second HKMG comprises a control gate.
8. The method according to claim 7 , further comprising:
forming source/drain regions in the substrate for the first gate-stack structure and the second gate-stack structure prior to forming the ILD.
9. The method according to claim 8 , further comprising:
forming a hard-mask layer over the first HKMG and the second HKMG; and
forming contacts on the source/drain regions through the ILD.
10. The method according to claim 6 , further comprising:
removing the second hard-mask, forming a second cavity, subsequent to forming the first HKMG;
removing an upper portion of the first HKMG in the first cavity, forming a third cavity; and
filling the second cavity and the third cavity with tungsten.
11. The method according to claim 10 , further comprising:
forming source/drain regions in the substrate for the first gate-stack structure and the second gate-stack structure prior to forming the ILD.
12. The method according to claim 11 , further comprising:
forming a hard-mask layer over the tungsten, the second cavity, and the third cavity; and
forming contacts on the source/drain regions through the ILD.