Mechanism to accelerate removal of store operations from a queue
View Patent ↗A processor includes at least one processing core. The processing core includes a memory cache, a store queue, and a post-retirement store queue. The processing core retires a store in the store queue and conveys the store to the memory cache and the post-retirement store queue, in response to retiring the store. In one embodiment, the store queue and/or the post-retirement store queue is a first-in, first-out queue. In a further embodiment, to convey the store to the memory cache, the processing core obtains exclusive access to a portion of the memory cache targeted by the store. The processing core buffers the store in a coalescing buffer and merges with the store, one or more additional stores and/or loads targeted to the portion of the memory cache targeted by the store prior to writing the store to the memory cache.
1. A processor comprising:
at least a first processing core, wherein the first processing core includes a memory cache, a store queue, and a post-retirement store queue;
wherein the first processing core is configured to:
retire a first store in the store queue; and
convey the first store to both the memory cache and the post-retirement store queue, in response to retiring the first store.
2. The processor of claim 1 , wherein at least one of the store queue and the post-retirement store queue is a first-in-first-out queue.
3. The processor of claim 1 , wherein to convey the first store to the memory cache, the first processing core is further configured to obtain exclusive access to a portion of the memory cache targeted by the first store.
4. The processor of claim 1 , wherein to convey the first store to the memory cache, the first processing core is further configured to:
buffer the first store in a coalescing buffer; and
merge with the first store, one or more additional stores and/or loads targeted to the portion of the memory cache targeted by the first store prior to writing the first store to the memory cache.
5. The processor of claim 1 , further comprising:
a second processing core; and
a shared memory shared by the first and second processing cores.
6. The processor of claim 5 , wherein the memory cache comprises a level-1 cache and the shared memory comprises a level-2 cache.
7. The processor of claim 5 , wherein the first processing core is further configured to convey the first store from the post-retirement queue to the shared memory.
8. The processor of claim 7 , wherein to convey the first store from the post-retirement store queue to the shared memory, the first processing core is further configured to obtain exclusive access to a portion of the shared memory targeted by the first store.
9. A store unit comprising:
a store queue; and
a post-retirement store queue;
wherein the store unit is configured to:
retire a first store in the store queue; and
convey the first store to both a memory cache and the post-retirement store queue, in response to retiring the first store.
10. The store unit of claim 9 , wherein to convey the first store to the memory cache, the store unit is further configured to obtain exclusive access to a portion of the memory cache targeted by the first store.
11. The store unit of claim 9 , wherein to convey the first store to the memory cache, the store unit is further configured to:
buffer the first store in a coalescing buffer; and
merge with the first store, one or more additional stores and/or loads targeted to the portion of the memory cache targeted by the first store prior to writing the first store to the memory cache.
12. The store unit of claim 9 , wherein the store unit is further configured to convey the first store from the post-retirement queue to a shared memory.
13. The store unit of claim 12 , wherein the memory cache comprises a level-1 cache and the shared memory comprises a level-2 cache.
14. The store unit of claim 12 , wherein to convey the first store from the post-retirement store queue to the shared memory, the store unit is further configured to obtain exclusive access to a portion of the shared memory targeted by the first store.
15. A method comprising:
retiring a first store in a store queue of a store unit;
conveying the first store to both a memory cache of the store unit and a post-retirement store queue of the store unit, in response to retiring the first store.
16. The method of claim 15 , wherein conveying the first store to the memory cache further comprises obtaining exclusive access to a portion of the memory cache targeted by the first store.
17. The method of claim 15 , wherein conveying the first store to the memory cache further comprises:
buffering the first store in a coalescing buffer; and
merging with the first store, one or more additional stores and/or loads targeted to the portion of the memory cache targeted by the first store prior to writing the first store to the memory cache.
18. The method of claim 15 , further comprising conveying the first store from the post-retirement queue to a shared memory.
19. The method of claim 18 , wherein the memory cache comprises a level-1 cache and the shared memory comprises a level-2 cache.
20. The method of claim 18 , wherein conveying the first store from the post-retirement store queue to the shared memory further comprises obtaining exclusive access to a portion of the shared memory targeted by the first store.