Method and system of automatic delay detection and receiver adjustment for synchronous bus interface
View Patent ↗An automatic delay detection and receiver adjustment method for a synchronous communications bus system sends a test pattern to the receivers of the system during a detection phase, uses the test pattern to determine a longest delay time for each bus lone, and adjusts a receiver for each bit line to receive incoming signals at a time based on the determined longest delay time.
1. A method of automatic delay detection and receiver adjustment for a synchronous communications bus system with multiple cycle delays, the method comprising the steps of:
(a) defining a delay detection and calibration phase for said synchronous communications bus system with multiple delays over multiple bus lines;
(b) sending during said delay detection and calibration phase a predefined bus signal test pattern for each bus line;
(c) using the predefined bus signal test pattern to determine a longest delay time for each bus line of said multiple bus lines during the delay detection and calibration phase;
(d) adjusting a receiver for each bit line of said multiple bus lines to receive incoming signals for each bus line at a time based on the determination of step (c); and after the detection and calibration phase is complete,
(e) placing the bus system in a normal communication mode.
2. In a synchronous communications bus system having a sender subsystem and a receiver subsystem having multiple bus lines, comprising:
an apparatus for detecting delay and adjusting all receivers in the receiving subsystem having multiple bus lines, the apparatus including worst case delay detection circuitry for each bit of the receiving subsystem bus lines; and
control circuitry coupled to the worst case delay detection circuitry for each bit; operative to select one of two receiver paths for each bit as a function of each bit's delay detection circuitry output and clock signals associated with each bit's receiver latch in the receiving subsystem.
3. The apparatus of claim 2 wherein at least two of the bits have worst case delay detection circuitry adapted to use different clock phases of the synchronous bus system.