Time stamping transactions to validate atomic operations in multiprocessor systems
View Patent ↗A multi-core microprocessor has a plurality of processor cores which are coupled to a bridge element. The bridge element sends transactions to and/or receives transactions from the processor cores, where each transaction has one or more packets. The transactions include atomic transactions. The bridge element comprises a buffer unit storing a time stamp for each packet sent or received. Furthermore, a multi-core multi-node processor system is provided that has debug hardware to capture and time stamp intra-node and/or inter-node transaction packets. Atomic operations are, for example, atomic read-modify-write instructions.
1. A multi-core microprocessor having a plurality of processor cores coupled to a bridge element, said bridge element configured to send transactions to and/or receive transactions from said processor cores, each transaction comprising one or more packets, said transactions including a transactions representing an atomic instructions, wherein said bridge element comprises a buffer unit configured to store a time stamp for each packet sent to and/or received from the processor cores;
wherein the multi-core microprocessor is configured to:
identify packets pertaining to a modifying atomic transaction and packets pertaining to other transactions;
compute, for each pair of packets built from one modifying atomic transaction and one other transaction, a probability value dependent on the time difference between the related time stamps;
compare the computed probability value with a threshold; and
indicate an error if the probability value exceeds said threshold.
2. The multi-core microprocessor of claim 1 , wherein said time stamp indicates the point of time at which the respective packet has been captured and stored in the buffer unit.
3. The multi-core microprocessor of claim 1 , wherein said other transactions overlap in time with the transaction representing the atomic instruction, wherein the multi-core microprocessor is adapted to identify said other transactions by evaluating the time stamps of their packets.
4. The multi-core microprocessor of claim 1 , wherein said other transactions are transactions updating the same coherency granule as the transaction representing the atomic instruction.
5. The multi-core microprocessor of claim 1 , adapted to determine said probability based on a normal distribution having distribution parameters being unique for each packet-to-packet relation.
6. The multi-core microprocessor of claim 5 , wherein said distribution parameters are selected in an iterative fine-tuning process that includes simulation and analysis of system data.
7. The multi-core microprocessor of claim 1 , adapted to detect an error in an atomic instruction by determining probability values for each pair of packets including a packet of the transaction representing the atomic instruction and a packet of another transaction overlapping in time with the transaction representing the atomic instruction, classifying the determined probability values by grouping them into a number of buckets representing different probability ranges, and determining whether the bucket representing the range of the highest probabilities is at least partly filled.
8. The multi-core microprocessor of claim 7 , adapted to determine, if no error is detected, a risk factor based on the classification into other buckets than the bucket representing the range of the highest probabilities, and start a simulation process dependent on the risk factor.
9. A multiprocessor system comprising:
a plurality of microprocessor nodes each having a plurality of microprocessor cores, the plurality of microprocessor nodes and cores being connected to form a transactional point-to-point communication network; and
debug hardware adapted to validate atomic operations, said debug hardware configured to capture and time stamp intra-node and/or inter-node transaction packets;
wherein the multiprocessor system is configured to:
identify packets pertaining to a modifying atomic transaction and packets pertaining to other transactions;
compute, for each pair of packets built from one modifying atomic transaction and one other transaction, a probability value dependent on the time difference between the related time stamps;
compare the computed probability value with a threshold; and
indicate an error if the probability value exceeds said threshold.
10. The multiprocessor system of claim 9 , wherein each microprocessor node further has a bridge element coupled to the microprocessor cores of the respective microprocessor node, and said debug hardware comprises a buffer in each bridge element for buffering time stamps of intra-node transaction packets.
11. A method of detecting errors caused by a modifying atomic transaction in a multi-core microprocessor environment, the method comprising:
collecting data relating to packets pertaining to said modifying atomic transaction and other transactions communicated between microprocessor cores of the environment;
processing the collected data, wherein processing the collected data comprises:
identifying packets pertaining to said modifying atomic transaction;
identifying packets pertaining to said other transactions; and
computing, for each pair of packets built from one packet of said modifying atomic transaction and one packet of said other transactions a probability value dependent on the time difference between the related time stamps; and
evaluating results of said processing, wherein said evaluating results comprises:
comparing the computed probability values with a threshold; and
indicate an error if at least one of the computed probability values exceeds said threshold;
wherein said data include time stamps indicating a point of time at which the respective packets have been transmitted between the respective microprocessor cores.
12. The method of claim 11 , wherein computing the probability value is based on a symmetric probability distribution function having its maximum when there is no time difference.
13. The method of claim 12 , wherein the height and shape of said symmetric probability distribution function depends on the pair of packets for which the probability value is computed.
14. The method of claim 11 , wherein identifying packets pertaining to said other transactions comprises:
selecting only those ones of said other transactions that update the same coherency granule as said modifying atomic transaction and that overlap in time with said modifying atomic transaction; and
identifying the packets pertaining to the selected transactions.
15. The method of claim 11 , wherein selecting the transactions comprises:
obtaining the time stamp of the respective ones of said other transactions and said modifying atomic transaction to determine whether the transactions overlap in time.
16. A multi-core microprocessor having a plurality of processor cores coupled to a bridge element, said bridge element configured to send transactions to and/or receive transactions from said processor cores, each transaction comprising one or more packets, said transactions including a transactions representing an atomic instructions, wherein said bridge element comprises a buffer unit configured to store a time stamp for each packet sent to and/or received from the processor cores, wherein the multi-core microprocessor is adapted to:
detect an error in an atomic instruction by determining probability values for each pair of packets including a packet of the transaction representing the atomic instruction and a packet of another transaction overlapping in time with the transaction representing the atomic instruction;
classify the determined probability values by grouping them into a number of buckets representing different probability ranges; and
determine whether the bucket representing the range of the highest probabilities is at least partly filled.