IP Library Granted Patent US 7,747,881
Granted Patent B2
US 7,747,881 · App. 11/503,700 · Granted Jun 29, 2010

System and method for limiting processor performance

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Quick Facts
Patent No.
US 7,747,881
App. No.
11/503,700
Granted
Jun 29, 2010
Kind
B2
Abstract

A system and method for managing performance states of a processor. An enclosure comprises a first processing board with a processor and a second processing board with a processor. A service processor may also be coupled to the enclosure via an interconnect. The second processing board is configured to store a value indicative of a maximum processor performance state for a processor on the second board. In response to a detected request for a transition to a first processor performance state, the processor on the second board is configured to transition to the first processor performance state, if the first processor state is less than or equal to the maximum processor performance state; and transition to the maximum processor performance state, if the first processor state is greater than the maximum processor state. The second processor board may store the value in response to a an operating environment condition detected elsewhere within the enclosure.

Claims (41)

1. A method for managing processor performance, the method comprising:

storing a value indicative of a maximum processor performance state;

detecting a request for a transition to a first processor performance state;

transitioning the processor to the first processor performance state, in response to determining the first processor state is less than or equal to the maximum processor performance state;

transitioning the processor to the maximum processor performance state, in response to determining the first processor state is greater than the maximum processor state; and

reporting to an operating system that the processor has transitioned to the first processor state, in response to determining the first processor state is greater than the maximum processor state.

2. The method as recited in claim 1 , wherein storing said value is responsive to a detected operating environment condition.

3. The method as recited in claim 2 , wherein said condition comprises a thermal condition.

4. The method as recited in claim 2 , further comprising:

detecting said operating environment condition in a first portion of an enclosure;

reporting the operating environment condition to a remote service processor;

conveying a command from the service processor to a second portion of the enclosure; and

storing the value responsive to receiving the command.

5. The method as recited in claim 4 , wherein said operating environment condition is not detected in said second portion of the enclosure.

6. The method as recited in claim 1 , wherein the value indicative of a processor performance state is stored in an externally accessible register of the processor.

7. A system for managing processor performance, the system comprising:

an enclosure comprising a first processing board which comprises a processor, and a second processing board which comprises a processor; and

a service processor coupled to the enclosure via an interconnect;

wherein the second processing board is configured to:

store a value indicative of a maximum processor performance state;

detect a request for a transition to a first processor performance state;

transition the processor in the second processing board to the first processor performance state, in response to determining the first processor state is less than or equal to the maximum processor performance state;

transition the processor in the second processing board to the maximum processor performance state, in response to determining the first processor state is greater than the maximum processor state; and

report to an operating system that the processor has transitioned to the first processor state, in response to determining the first processor state is greater than the maximum processor state.

8. The system as recited in claim 7 , wherein the value stored in the second processing board is responsive to a detected operating environment condition.

9. The system as recited in claim 8 , wherein said condition comprises a thermal condition.

10. The system as recited in claim 8 , wherein the operating environment condition is detected by the first processing board and reported to the service processor, and wherein in response to the reported condition, the service processor conveys a command to the second processing board which is configured to store the value responsive to receiving the command.

11. The system as recited in claim 10 , wherein said operating environment condition is not detected in said second portion of the enclosure.

12. The system as recited in claim 7 , wherein the value indicative of a processor performance state is stored in an externally accessible register of the processor on the second board.

13. A system for managing processor performance, the system comprising:

a controller configured to monitor operating environment conditions; and

a processor comprising an externally accessible register, wherein the processor is configured to:

detect a request for a transition to a first processor performance state;

access the register to determine a maximum processor performance state;

transition the processor to the first processor performance state, in response to determining the first processor state is less than or equal to the maximum processor performance state;

transition the processor to the maximum processor performance state, in response to determining the first processor state is greater than the maximum processor state; and

report to an operating system that the processor has transitioned to the first processor state, in response to determining the first processor state is greater than the maximum processor state.

14. The system as recited in claim 13 , wherein the controller is configured to store a value indicative of the maximum processor performance state responsive to a detected operating environment condition.

15. The system as recited in claim 14 , wherein said condition comprises a thermal condition.

16. The system as recited in claim 13 , wherein the operating environment condition is detected by a device external to the processor and controller, and wherein the controller is configured to store said value in response to a command received from a service processor.

17. The system as recited in claim 13 , wherein the controller comprises a baseboard management controller.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded May 12, 2021
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 056987/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 29, 2021
From: GLOBALFOUNDRIES US INC.
To: MEDIATEK INC.
Reel/Frame 055173/0781 →
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054636/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2020
From: GLOBALFOUNDRIES INC.
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 054633/0001 →
SECURITY AGREEMENT Recorded Nov 29, 2018
From: GLOBALFOUNDRIES INC.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 049490/0001 →
AFFIRMATION OF PATENT ASSIGNMENT Recorded Aug 18, 2009
From: ADVANCED MICRO DEVICES, INC.
To: GLOBALFOUNDRIES INC.
Reel/Frame 023120/0426 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 14, 2006
From: DURAN, FRANCISCO L.; MONTGOMERY, W. PAUL; TOBIAS, DAVID F.
To: ADVANCED MICRO DEVICES, INC.
Reel/Frame 018177/0094 →