Data processor having a cache with efficient storage of predecode information, cache, and method
View Patent ↗A data processor ( 200 ) includes an instruction cache ( 220 ) and a secondary cache ( 250 ). The instruction cache ( 220 ) has a plurality of cache lines. Each of the plurality of cache lines stores a first plurality of bits ( 222 ) corresponding to at least one instruction and a second plurality of bits ( 224, 226 ) associated with the execution of the at least one instruction. The secondary cache ( 250 ) is coupled to the instruction cache ( 220 ) and stores cache lines from the instruction cache ( 250 ) by storing the first plurality of bits ( 222 ) and a third plurality of bits ( 255, 257 ) corresponding to the second plurality of bits ( 224, 226 ). The third plurality of bits ( 255, 257 ) is fewer in number than the second plurality of bits ( 224, 226 ).
1. A data processor comprising:
a first cache comprising a first line, wherein the first line includes a first field that stores a first data representative of a set of one or more instructions and a second field that stores bits representing branch prediction information for the set of one or more instructions; and
a compressor configured to:
obtain a first set of bits representing a first branch prediction information for the set of one or more instructions, wherein the first branch prediction information represents, for each branch instruction of the set of one or more instructions, a branch type of the branch instruction and taken or not taken history information, the branch type comprising one selected from a call instruction type; a return instruction type; a static branch type; and a dynamic branch type; and
compress the first set of bits to generate a second set of bits for storage in the second field, the second set of bits representing a second branch prediction information for the set of one or more instructions, the second branch prediction information comprising only a subset of the first branch prediction information and the second set of bits comprising fewer bits than the first set of bits, wherein the second branch prediction information represents, for each branch instruction of the set of one or more instructions, whether the branch instruction is a static branch or a dynamic branch.
2. The data processor of claim 1 , wherein each bit of the second set of bits is associated with a corresponding branch instruction of the subset of the branch instructions and represents whether the corresponding branch instruction is a static branch or a dynamic branch.
3. The data processor of claim 1 , wherein the compressor is configured to generate the second set of bits so as to represent branch prediction information for only a subset of the branch instructions of the set of one or more instructions in response to determining a number of branch instructions in the set of one or more instructions is greater than a select number.
4. The data processor of claim 3 , wherein the compressor is configured to generate the second set of bits so as to represent a type of branch of each branch instruction in the set of one or more instructions in response to determining the number of branch instructions in the set of one or more instructions is not greater than the select number.
5. The data processor of claim 4 , wherein the type of branch of each branch instruction comprises one selected from a group consisting of: a call instruction type; a return instruction type; a static branch type; and a dynamic branch type.
6. A method comprising:
storing a first data representative of a set of one or more instructions at a first field of a first line of a first cache;
receiving a first set of bits representing a first branch prediction information for the set of one or more instructions, wherein the first branch prediction information represents, for each branch instruction of the set of one or more instructions, a branch type of the branch instruction and taken or not taken history information, the branch type comprising one selected from a call instruction type; a return instruction type; a static branch type; and a dynamic branch type; and
generating a second set of bits for storage at a second field of the first line of the first cache, the second set of bits representing a second branch prediction information for the set of one or more instructions, the second branch prediction information comprising only a subset of the first branch prediction information and the second set of bits comprising fewer bits than the first set of bits, wherein the second branch prediction information represents, for each branch instruction of the set of one or more instructions, whether the branch instruction is a static branch or a dynamic branch.
7. The method of claim 6 , wherein each bit of the second set of bits is associated with a corresponding branch instruction of the subset of the branch instructions and represents whether the corresponding branch instruction is a static branch or a dynamic branch.
8. The method of claim 6 , wherein generating the second set of bits comprises generating the second set of bits so as to represent branch prediction information for only a subset of the branch instructions of the set of one or more instructions in response to determining a number of branch instructions in the set of one or more instructions is greater than a select number.
9. The method of claim 8 , wherein generating the second set of bits generating the second set of bits so as to represent a type of branch of each branch instruction in the set of one or more instructions in response to determining the number of branch instructions in the set of one or more instructions is not greater than the select number.
10. The method of claim 9 , wherein the type of branch of each branch instruction comprises one selected from a group consisting of: a call instruction type; a return instruction type; a static branch type; and a dynamic branch type.
11. A data processor comprising:
a first cache comprising a first line, wherein the first line includes a first field that stores a first data representative of a set of one or more instructions and a second field that stores bits representing branch prediction information for the set of one or more instructions; and
a compressor configured to:
obtain a first set of bits representing a first branch prediction information for the set of one or more instructions, the first branch prediction information comprising a first amount of branch prediction information for each branch instruction of the set of one or more instructions and the first amount of branch prediction information for each branch instruction representing a branch type of the branch instruction and taken or not taken history information, the branch type comprising one selected from a call instruction type; a return instruction type; a static branch type; and a dynamic branch type; and
compress the first set of bits to generate a second set of bits for storage in the second field, the second set of bits representing a second branch prediction information for the set of one or more instructions, the second branch prediction information comprising only a subset of the first branch prediction information and the second set of bits comprising fewer bits than the first set of bits, the second branch prediction information comprising a second amount of branch prediction information for each branch instruction of the set of one or more instructions, the second amount less than the first amount and the second amount of branch prediction information for each branch instruction represents whether the branch instruction is a static branch or a dynamic branch.
12. The data processor of claim 11 , wherein each bit of the second set of bits is associated with a corresponding branch instruction of the subset of the branch instructions and represents whether the corresponding branch instruction is a static branch or a dynamic branch.
13. The data processor of claim 11 , wherein the compressor is further configured to generate the second set of bits to represent branch prediction information for only a subset of the branch instructions of the set of one or more instructions in response to determining a number of branch instructions in the set of one or more instructions is greater than a select number.
14. The data processor of claim 13 , wherein the compressor is further configured to generate the second set of bits to represent a type of branch of each branch instruction in the set of one or more instructions in response to determining the number of branch instructions in the set of one or more instructions is not greater than the select number.
15. The data processor of claim 14 , wherein the type of branch of each branch instruction comprises one selected from a group consisting of: a call instruction type; a return instruction type; a static branch type; and a dynamic branch type.
16. A method comprising:
storing a first data representative of a set of one or more instructions at a first field of a first line of a first cache;
receiving a first set of bits representing a first branch prediction information for the set of one or more instructions, the first branch prediction information comprising a first amount of branch prediction information for each branch instruction of the set of one or more instructions and the first amount of branch prediction information for each branch instruction representing a branch type of the branch instruction and taken or not taken history information, the branch type comprising one selected from a call instruction type; a return instruction type; a static branch type; and a dynamic branch type; and
generating a second set of bits for storage at a second field of the first line of the first cache, the second set of bits representing a second branch prediction information for the set of one or more instructions, the second branch prediction information comprising only a subset of the first branch prediction information and the second set of bits comprising fewer bits than the first set of bits, the second branch prediction information comprising a second amount of branch prediction information for each branch instruction of the set of one or more instructions, the second amount less than the first amount and the second amount of branch prediction information for each branch instruction represents whether the branch instruction is a static branch or a dynamic branch.
17. The method of claim 16 , wherein each bit of the second set of bits is associated with a corresponding branch instruction of the subset of the branch instructions and represents whether the corresponding branch instruction is a static branch or a dynamic branch.
18. The method of claim 16 , wherein generating the second set of bits includes generating the second set of bits so as to represent branch prediction information for only a subset of the branch instructions of the set of one or more instructions in response to determining a number of branch instructions in the set of one or more instructions is greater than a select number.
19. The method of claim 18 , wherein generating the second set of bits includes generating the second set of bits so as to represent a type of branch of each branch instruction in the set of one or more instructions in response to determining the number of branch instructions in the set of one or more instructions is not greater than the select number.
20. The method of claim 19 , wherein the type of branch of each branch instruction comprises one selected from a group consisting of: a call instruction type; a return instruction type; a static branch type; and a dynamic branch type.