Granted Patent B1

US 7,373,484 · App. 10/755,692 · Granted May 13, 2008

Abstract

Claims (29)

1. A method of controlling write operations to a non-renamed register space of an out-of-order execution processor, said method comprising:

receiving a write operation to a given register within said non-renamed register space;

checking a bit that corresponds to said given register, and that indicates whether a pending write operation to said given register exists;

blocking said write operation to said given register from being scheduled in response to said bit indicating that said pending write operation to said given register exists;

allowing said write operation to said given register to be scheduled in response to said bit indicating that said pending write operation to said given register does not exist;

allowing a subsequent write operation to a different register within said non-renamed register space to be scheduled in response to a different bit indicating that a pending write operation to said different register does not exist; and

causing said bit that corresponds to said given register to indicate that said pending write operation to said given register does not exist in response to detecting that said pending write operation to said given register is an oldest operation scheduled for execution but has not issued to an execution unit for execution.

2. The method as recited in claim 1 further comprising providing a storage including a plurality of bits each corresponding to a respective register within said non-renamed register space.

3. The method as recited in claim 1 , further comprising asserting said bit that corresponds to said given register in response to receiving said write operation to said given register.

4. The method as recited in claim 1 , further comprising deasserting said bit that corresponds to said given register in response to detecting that said pending write operation to said given register is an oldest operation scheduled but has not issued to an execution unit for execution.

5. The method as recited in claim 1 further comprising preventing a received read operation to said given register from being scheduled in response to determining that said pending write operation to said given register exists.

6. The method as recited in claim 5 further comprising allowing said received read operation to be scheduled in response to detecting that said pending write operation to said given register is an oldest operation scheduled for but has not issued to an execution unit for execution.

7. The method as recited in claim 1 , wherein each of said non-renamed registers is a segment register.

8. A processor including a plurality of non-renamed registers, said processor comprising:

an execution unit;

a scheduler coupled to said execution unit and configured to schedule and issue instructions for execution by said execution unit; and

an instruction control unit coupled to said scheduler and configured to:

receive a write operation to a given non-renamed register;

check a bit that corresponds to said given non-renamed register, and that indicates whether a pending write operation to said given non-renamed register exists;

block said write operation to said given non-renamed register from being scheduled in response to said bit indicating that said pending write operation to said given non-renamed register exists;

allow said write operation to said given non-renamed register to be scheduled in response to said bit indicating that said pending write operation to said given non-renamed register does not exist;

allow a subsequent write operation to a different non-renamed register to be scheduled in response to a different bit indicating that a pending write operation to said different non-renamed register does not exist; and

cause said bit that corresponds to said given register to indicate that said pending write operation to said given non-renamed register does not exist in response to detecting that said pending write operation to said given register is an oldest operation scheduled for execution but has not issued to the execution unit for execution.

9. The processor as recited in claim 8 , wherein said instruction control unit includes a storage including a plurality of bits each corresponding to a respective non-renamed register.

10. The processor as recited in claim 8 , wherein said instruction control unit is further configured to assert said bit that corresponds to said given non-renamed register in response to receiving said write operation to said given register.

11. The processor as recited in claim 8 , wherein said instruction control unit is further configured to deassert said bit that corresponds to said given non-renamed register in response to detecting that said pending write operation to said given non-renamed register is an oldest operation scheduled for execution but has not issued to the execution unit.

12. The processor as recited in claim 8 , wherein said instruction control unit is further configured to prevent a received read operation to said given non-renamed register from being scheduled in response to determining that said pending write operation to said given non-renamed register exists.

13. The processor as recited in claim 12 , wherein said instruction control unit is further configured to allow said received read operation to be scheduled in response to detecting that said pending write operation to said given non-renamed register is an oldest operation scheduled for execution but has not issued to the execution unit.

14. The processor as recited in claim 8 , wherein each of said non-renamed registers is a segment register.

Assignments (6)