Etch stop layer for a metallization layer with enhanced etch selectivity and hermeticity
View Patent ↗By providing a barrier layer stack including a silicon nitride layer for confining a copper-based metal region, thereby also effectively avoiding any diffusion of oxygen and moisture into the copper region, and a nitrogen-enriched silicon carbide layer, the total relative permittivity may be maintained at a low level, since the thickness of the silicon nitride layer may be moderately thin, while the relatively thick silicon carbide nitride layer provides the required high etch selectivity during a subsequent patterning process of the low-k dielectric layer.
1. A method, comprising:
forming a dielectric barrier layer stack over a substrate having formed thereon a metal region, said dielectric barrier layer stack comprising a first dielectric layer having a first thickness and a first relative permittivity and being formed on said metal region, said dielectric barrier layer stack further comprising a second dielectric layer formed on said first dielectric layer, said second dielectric layer having a first nitrogen content, a second relative permittivity, and a second thickness, said second thickness being greater than said first thickness, said second relative permittivity being less than said first relative permittivity;
forming a third dielectric layer above said second dielectric layer, said third dielectric layer having a second nitrogen content less than the first nitrogen content; and
forming a low-k dielectric layer over said dielectric barrier layer stack.
2. The method of claim 1 , wherein forming said dielectric layer stack comprises depositing said first, second, and third dielectric layers in situ.
3. The method of claim 2 , wherein said first dielectric layer is deposited on the basis of a first plasma ambient comprising silane and a nitrogen-containing precursor.
4. The method of claim 3 , wherein said second dielectric layer is deposited on the basis of a second plasma ambient comprising a silane-containing precursor and ammonia (NH 3 ).
5. The method of claim 1 , wherein forming said dielectric layer stack comprises controlling said first thickness on the basis of a first target value ranging from approximately 5-20 nm and controlling said second thickness on the basis of a second target value ranging from approximately 30-90 nm.
6. The method of claim 2 , wherein depositing said first, second, and third dielectric layers in situ includes substantially preventing ambient air to come into contact with said substrate prior to completely depositing said third dielectric layer.
7. The method of claim 1 , further comprising forming said third dielectric layer so as to have a reduced nitrogen concentration at an interface located proximal to said low-k dielectric layer.
8. The method of claim 1 , wherein said third dielectric layer has a thickness less than said second dielectric layer.
9. The method of claim 1 , further comprising etching an opening through said low-k dielectric layer and using said dielectric layer stack for controlling said etch process.
10. The method of claim 1 , wherein the first dielectric layer comprises silicon nitride.
11. The method of claim 10 , wherein the second dielectric layer comprises nitrogen-containing silicon carbide.
12. The method of claim 1 , wherein the second dielectric layer comprises nitrogen-containing silicon carbide.
13. The method of claim 1 , wherein said third dielectric layer comprises silicon carbide.
14. The method of claim, 1 , wherein the first dielectric layer comprises silicon nitride, the second dielectric layer comprises nitrogen-containing silicon carbide, and the third dielectric layer comprises non-nitrogen-containing silicon carbide.