Self-aligned dual stressed layers for NFET and PFET
View Patent ↗Methods are disclosed for forming self-aligned dual stressed layers for enhancing the performance of NFETs and PFETs. In one embodiment, a sacrificial layer is used to remove a previously deposited stressed layer. A mask position used to pattern the sacrificial layer is adjusted such that removal of the latter deposited stressed layer, using the sacrificial layer, leaves the dual stress layers in an aligned form. The methods result in dual stressed layers that do not overlap or underlap, thus avoiding processing problems created by those issues. A semiconductor device including the aligned dual stressed layers is also disclosed.
1. A method for forming a self-aligned dual stressed layer for a semiconductor device having an NFET and a PFET, the method comprising the steps of:
forming a first stressed silicon nitride layer over a first one of the NFET and the PFET, the first stressed silicon nitride layer including an end over a portion of an intermediate region between the NFET and the PFET;
depositing a second stressed silicon nitride layer over the NFET, the PFET and the intermediate region, the second stressed silicon nitride layer forming a first shoulder over the end of the first stressed silicon nitride layer;
forming a sacrificial layer over the second stressed silicon nitride layer, the sacrificial layer forming a second shoulder over the first shoulder;
forming a mask over the sacrificial layer and a second one of the NFET and the PFET such that a mask edge is between the first shoulder and the second shoulder;
removing the sacrificial layer over the first one of the NFET and the PFET using the mask;
removing the mask; and
removing the second stressed silicon nitride layer over the first one of the NFET and the PFET.
2. The method of claim 1 , wherein the sacrificial layer forming step includes forming a second shoulder over the first shoulder, and
wherein the mask forming step includes forming the mask such that the mask covers the second shoulder.
3. The method of claim 1 , wherein the first stressed silicon nitride layer forming step includes:
depositing the first stressed silicon nitride layer over the NFET, the PFET and the intermediate region;
forming a mask over the first stressed silicon nitride layer such that a second one of the NFET and PFET is exposed; and
removing the first stressed silicon nitride layer from over the second one of the NFET and the PFET.
4. The method of claim 1 , wherein the sacrificial layer has a thickness of no less than approximately 70 nm and no greater than approximately 100 nm.
5. The method of claim 1 , wherein the mask forming step includes:
forming the mask over the sacrificial layer such that the mask edge is distanced from the first shoulder; and
etching to move the mask edge closer to the first shoulder.
6. The method of claim 1 , further comprising removing the sacrificial layer over the second one of the NFET and the PFET.
7. The method of claim 1 , further comprising the step of depositing an etch stop layer over the first stressed silicon nitride layer.
8. The method of claim 1 , wherein the first one is the NFET and the first stressed silicon nitride layer is a tensile silicon nitride, and the second one is the PFET and the second stressed silicon nitride layer is a compressive silicon nitride.
9. The method of claim 1 , wherein the end is positioned over a trench isolation.
10. The method of claim 1 , wherein the sacrificial layer includes silicon dioxide.
11. A method for self-aligning stressed layers for a semiconductor device having an NFET and a PFET, the method comprising the steps of:
forming a first stressed layer over a first one of the NFET and PFET;
depositing a second stressed layer over the NFET and the PFET, the second stressed layer having a first shoulder where the second stressed layer extends over an end of the first stressed layer;
forming a sacrificial layer over the second stressed layer, the sacrificial layer having a second shoulder where the sacrificial layer extends over the first shoulder;
forming a mask over a second one of the NFET and the PFET such that a mask edge is one of over the second shoulder and nearly aligned with the first shoulder;
removing the sacrificial layer over the first one of the NFET and the PFET using the mask;
removing the mask; and
removing the second stressed layer over the first one of the NFET and the PFET.
12. The method of claim 11 , wherein the sacrificial layer forming step includes forming a second shoulder over the first shoulder, and
wherein the mask forming step includes forming the mask edge such that the mask edge covers the second shoulder.
13. The method of claim 11 , wherein the first stressed layer forming step includes:
depositing the first stressed layer over the NFET, the PFET and the intermediate region;
forming a mask over the first stressed layer such that the second one of the NFET and PFET is exposed; and
removing the first stressed layer from over the second one of the NFET and the PFET.
14. The method of claim 11 , wherein the sacrificial layer has a thickness of no less than approximately 70 nm and no greater than approximately 100 nm.
15. The method of claim 11 , wherein the mask forming step includes:
forming the mask over the sacrificial layer such that the mask edge is distanced from the first shoulder; and
etching to move the mask edge closer to the first shoulder.
16. The method of claim 11 , further comprising removing the sacrificial layer over the second one of the NFET and the PFET.
17. The method of claim 11 , further comprising the step of depositing an etch stop layer over the flit stressed layer.
18. The method of claim 11 , wherein the intermediate region is positioned over a trench isolation.
19. The method of claim 11 , wherein the fist and second stressed layers include silicon nitride.