Bit line implant
View Patent ↗A method for performing a bit line implant is disclosed. The method includes forming a group of structures on an oxide-nitride-oxide stack of a semiconductor device. Each structure of the group of structures includes a polysilicon portion and a hard mask portion. A first structure of the group of structures is separated from a second structure of the group of structures by less than 100 nanometers. The method further includes using the first structure and the second structure to isolate a portion of the semiconductor device for the bit line implant.
1. A method of performing a bit line implant, the method comprising:
forming a first structure and a second structure on an oxide-nitride-oxide stack on a substrate of a semiconductor device, the first structure and the second structure each including a polysilicon portion and a hard mask portion, the hard mask portions including opposing sidewalls, wherein the first structure and the second structure are separated by a gap having a width ranging from about 500 to about 1,000 Å;
forming a first spacer adjacent a sidewall of the hard mask portion of the first structure and a second spacer adjacent a sidewall of the hard mask portion of the second structure;
etching, using the first and second spacers, the oxide-nitride-oxide stack to form a trench to a width ranging from about 40 to about 70 nanometers to expose a top surface of a portion of the substrate; and
implanting, in the trench, a dopant at a dosage ranging from about 1×10 12 atoms/cm 2 to about 1×10 15 atoms/cm 2 and an implantation energy ranging from about 5 KeV to about 30 KeV.
2. The method of claim 1 wherein the forming a first structure and a second structure includes:
forming the hard mask portion to a thickness ranging from about 400 Å to about 1,000 Å, and
forming the polysilicon portion to a thickness ranging from about 500 Å to about 1,200 Å.
3. The method of claim 2 wherein the forming a first structure and a second structure includes:
forming the hard mask portion to a width ranging from about 800 Å to about 1,600 Å, and
forming the polysilicon portion to a width ranging from about 1,000 Å to about 1,800 Å.
4. The method of claim 1 wherein the trench is formed to a width ranging from about 40 nanometers to about 50 nanometers.
5. A semiconductor device comprising:
an oxide-nitride-oxide stack formed on a substrate,
first conductive structures formed on the oxide-nitride-oxide stack, the first conductive structures serving as a bit line implant blocker, the first conductive structures having facing sidewalls separated by less than 100 nanometers from each other;
a second conductive layer formed on the first conductive structures, the second conductive layer serving as a word line;
spacers formed along the facing sidewalls of the first conductive structures to a thickness from about 100 Å to about 250 Å; and
a high density plasma oxide formed in a gap between the spacers, the gap being of a thickness from about 40 nanometers to about 70 nanometers.
6. A method comprising:
forming a polysilicon layer on an oxide-nitride-oxide stack on a substrate;
forming hard mask structures on the polysilicon layer, the hard mask structures including sidewalls facing each other;
forming first sidewall spacers adjacent to the facing sidewalls of the hard mask structures;
etching the polysilicon layer using the first sidewall spacers to form a first polysilicon structure with a first sidewall and a second polysilicon structure with a second sidewall and to expose a top surface of the oxide-nitride-oxide stack, the first polysilicon structure being separated by a distance less than 100 nanometers apart from the second polysilicon structure, the first and second sidewalls face each other;
forming second sidewall spacers adjacent to the first and second sidewalls;
etching the oxide-nitride-oxide stack using the first sidewall spacers and the second sidewall spacers to form a trench to expose the substrate, the trench being formed to a width ranging from about 40 nanometers to about 70 nanometers; and
performing a bit line implant in the trench.
7. The method of claim 6 , the performing a bit line implant further comprising:
implanting a dopant at a dosage ranging from about 1×10 12 atoms/cm 2 to about 1×10 15 atoms/cm 2 and an implantation energy ranging from about 5 KeV to about 30 KeV in the trench.
8. The method of claim 6 wherein the hard mask structures comprise a silicon rich nitride, a silicon nitride, or a silicon oxynitride.
9. The method of claim 6 wherein the forming the plurality of hard mask structures includes:
forming the hard mask structures-to a thickness ranging from about 400 Å to about 1,000 Å, and
where the forming the polysilicon layer includes:
forming the polysilicon layer to a thickness ranging from about 500 Å to about 1,200 Å.
10. The method of claim 9 wherein the etching the polysilicon layer includes:
forming the first and second polysilicon structures each to a width ranging from about 1,000 Å to about 1,800 Å.
11. The method of claim 6 wherein the trench is formed to a width ranging from about 40 nanometers to about 50 nanometers.
12. The method of claim 6 further comprising:
filling, after the bit line implant, the trench with an oxide using a high density plasma process.
13. The method of claim 12 further comprising:
forming, after the filling, a word line above the first and second polysilicon structures.