Low-power multiple-channel fully depleted quantum well CMOSFETs
View Patent ↗A multiple-channel semiconductor device has fully or partially depleted quantum wells and is especially useful in ultra large scale integration devices, such as CMOSFETs. Multiple channel regions are provided on a substrate with a gate electrode formed on the uppermost channel region, separated by a gate oxide, for example. The vertical stacking of multiple channels and the gate electrode permit increased drive current in a semiconductor device without increasing the silicon area occupied by the device.
1. A multiple-channel semiconductor device, comprising:
a substrate;
source and drain extensions formed in said substrate;
a stack of layers overlying said substrate in the following sequence:
a first insulator layer on the substrate, wherein the source and drain extensions are formed below the first insulator layer;
a first channel region on the first insulator layer;
a second insulator layer on the first channel region;
a second channel region on the second insulator layer;
a third insulator layer on the second channel region; and
a gate electrode on the third insulator layer.
2. The device of claim 1 , wherein the first and second channel regions are lightly doped with a first conductivity type of dopant.
3. The device of claim 2 , wherein the gate electrode is heavily doped with a second conductivity type of dopant different than the first conductivity type.
4. The device of claim 3 , wherein the first and second channel regions and the gate electrode are doped silicon.
5. The device of claim 4 , further comprising doped silicon spacers on the substrate and forming sidewall spacers contacting the first and second channel regions.
6. The device of claim 5 , further comprising thermal oxide on sidewalls of the gate electrode.
7. The device of claim 5 , further comprising CVD oxide on sidewalls of the gate electrode.
8. The device of claim 4 , further comprising raised source and drain regions on the substrate and contacting the first and second channel regions.
9. The device of claim 1 , wherein the insulator layers are oxide.
10. The device of claim 1 wherein the channel regions are SiGe.
11. The device of claim 1 , wherein the gate electrode is doped SiGe.
12. The device of claim 1 , wherein the gate electrode is at least one of a metal or a silicide.