Semiconductor substrate layer configured for inducement of compressive or expansive force
View Patent ↗An integrated circuit (IC) utilizes a strained layer. The substrate can utilize trenches in a base layer to induce stress in a layer. The trenches define pillars on a back side of a bulk substrate or base layer of a semiconductor-on-insulator (SOI) wafer.
1. A substrate comprising:
a strained layer having a relatively planar top surface and a relatively planar bottom surface; and
a base layer below the relatively planar bottom surface of the strained layer, the base layer having trenches on a side opposite the strained layer, the trenches inducing stress in the strained layer.
2. The substrate of claim 1 , wherein the strained layer is a strained silicon.
3. The substrate of claim 1 , further comprising a compressive material in the trenches.
4. The substrate of claim 1 , further comprising a buried oxide layer between the base layer and the strained layer.
5. An IC substrate comprising:
a strained semiconductor layer having a relatively parallel top and bottom surfaces; and
a base layer, the base layer including a plurality of trenches and a compressive material disposed in the trenches, the trenches being formed on a second side of the base layer opposite a first side of the base layer, the second side being farther from the strained semiconductor layer than the first side.
6. The substrate of claim 5 , further comprising a liner in the trenches.
7. The substrate of claim 6 further comprising a mechanical compressive force on the base layer.
8. The substrate of claim 5 , wherein the trenches are in a waffle pattern.
9. The substrate of claim 5 , wherein the compressive material is a low thermal resistance material.
10. The substrate of claim 5 , wherein the compressive material includes nitride.
11. The substrate of claim 5 , wherein a buried oxide layer is between the base layer and the strained semiconductor layer.
12. The substrate of claim 5 , wherein the semiconductor layer is silicon.
13. A substrate for an integrated circuit including a strained layer, comprising:
a base layer;
an insulating layer above the base layer;
a semiconductor layer above the insulating layer, the semiconductor layer having a relatively planar bottom surface and a relatively planar top surface, the relatively planar top surface being for formation of active devices; and
a plurality of pillars in the base layer, the pillars being formed on a first side of the base layer opposite from a second side of the base layer, the second side being closer to the bottom surface than the first side.
14. The substrate of claim 13 , wherein the base layer includes a compressive material in apertures associated with the pillars.
15. The substrate of claim 14 , wherein the compressive material is planarized until the base layer is reached.
16. The substrate of claim 13 , wherein the semiconductor layer includes silicon.
17. The substrate of claim 13 , wherein the insulative layer includes silicon dioxide.
18. The substrate of claim 13 , wherein the base layer includes silicon.
19. The substrate of claim 13 , wherein the pillars have a width of 2000-3000 Å.
20. The substrate of claim 13 , wherein the compressive material includes nitride.