IP Library Granted Patent US 6,919,592
Granted Patent B2
US 6,919,592 · App. 09/915,093 · Granted Jul 19, 2005

Electromechanical memory array using nanotube ribbons and method for making same

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Quick Facts
Patent No.
US 6,919,592
App. No.
09/915,093
Granted
Jul 19, 2005
Kind
B2
Abstract

Electromechanical circuits, such as memory cells, and methods for making same are disclosed. The circuits include a structure having electrically conductive traces and supports extending from a surface of the substrate, and nanotube ribbons suspended by the supports that cross the electrically conductive traces, wherein each ribbon comprises one or more nanotubes. The electro-mechanical circuit elements are made by providing a structure having electrically conductive traces and supports, in which the supports extend from a surface of the substrate. A layer of nanotubes is provided over the supports, and portions of the layer of nanotubes are selectively removed to form ribbons of nanotubes that cross the electrically conductive traces. Each ribbon includes one or more nanotubes.

Claims (42)

1. An electromechanical circuit, comprising:

a structure having electrically conductive traces and supports extending from a surface of a substrate; and

nanotube ribbons suspended by the supports that cross the electrically conductive traces, wherein each ribbon has a cross-sectional area that is substantially rectangular.

2. The circuit of claim 1 wherein the electrically conductive traces are doped silicon traces.

3. The circuit of claim 1 wherein the electrically conductive traces are nanotubes.

4. The circuit of claim 1 wherein the electrically conductive traces are ribbons of nanotubes.

5. The circuit of claim 1 wherein the supports are rows of material and wherein the traces are substantially parallel to the rows.

6. The circuit of claim 5 wherein the traces are separated from the supports.

7. The circuit of claim 5 wherein the traces contact the supports.

8. The circuit of claim 1 wherein the supports are made from silicon nitride.

9. The circuit of claim 1 wherein the electrically conductive traces are over a layer of insulating material to electrically isolate the traces relative to one another.

10. The circuit of claim 1 wherein the electrically conductive traces are each over insulating material to electrically isolate the traces.

11. The circuit of claim 1 wherein ribbons are of a non-woven fabric of nanotubes.

12. The circuit of claim 1 wherein the ribbons are substantially a monolayer of nanotubes.

13. An electromechanical circuit, comprising:

a structure having electrically conductive traces and supports extending from a surface of a substrate; and

nanotube ribbons suspended by the supports that cross the electrically conductive traces, wherein each ribbon is flat.

14. The circuit of claim 13 wherein the electrically conductive traces are doped silicon traces.

15. The circuit of claim 13 wherein the electrically conductive traces are nanotubes.

16. The circuit of claim 13 wherein the electrically conductive traces are ribbons of nanotubes.

17. The circuit of claim 13 wherein the supports are rows of material and wherein the traces are substantially parallel to the rows.

18. The circuit of claim 13 wherein the traces are separated from the supports.

19. The circuit of claim 13 wherein the traces contact the supports.

20. The circuit of claim 13 wherein the supports are made from silicon nitride.

21. The circuit of claim 13 wherein the electrically conductive traces are over a layer of insulating material to electrically isolate the traces relative to one another.

22. The circuit of claim 13 wherein the electrically conductive traces are each over insulating material to electrically isolate the traces.

23. The circuit of claim 13 wherein ribbons are of a non-woven fabric of nanotubes.

24. The circuit of claim 13 wherein the ribbons are substantially a monolayer of nanotubes.

25. An electromechanical circuit, comprising:

a structure having electrically conductive traces and supports extending from a surface of a substrate; and

nanotube ribbons suspended by the supports that cross the electrically conductive traces, wherein each ribbon comprises a plurality of nanotubes.

26. The circuit of claim 25 wherein the electrically conductive traces are doped silicon traces.

27. The circuit of claim 25 wherein the electrically conductive traces are nanotubes.

28. The circuit of claim 25 wherein the electrically conductive traces are ribbons of nanotubes.

29. The circuit of claim 25 wherein the supports are rows of material and wherein the traces are substantially parallel to the rows.

30. The circuit of claim 25 wherein the traces are separated from the supports.

31. The circuit of claim 25 wherein the traces contact the supports.

32. The circuit of claim 25 wherein the supports are made from silicon nitride.

33. The circuit of claim 25 wherein the electrically conductive traces are over a layer of insulating material to electrically isolate the traces relative to one another.

34. The circuit of claim 25 wherein the electrically conductive traces are each over insulating material to electrically isolate the traces.

35. The circuit of claim 25 wherein ribbons are of a non-woven fabric of nanotubes.

36. The circuit of claim 25 wherein the ribbons are substantially a monolayer of nanotubes.

Assignments (2)
RELEASE OF SECURITY INTEREST IN PATENTS Recorded Jul 8, 2021
From: SILICON VALLEY BANK
To: NANTERO, INC.
Reel/Frame 056790/0001 →
INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Nov 11, 2020
From: NANTERO, INC.
To: SILICON VALLEY BANK
Reel/Frame 054383/0632 →