Digital phase locked loop for regenerating the clock of an embedded signal
View Patent ↗The present invention relates to a system and method for generating a first clock frequency for a plurality of digital data bursts compressed in time, where each of the plurality of digital data bursts has been multiplexed into one of a plurality of data blocks of higher speed digital data. The system and method includes acquiring the width in data elements of a digital data burst and the width in data elements of a data block of higher speed digital data. The width of one period of a clock pulse is computed at the first clock frequency. A clock pulse is generated at the first clock frequency.
1. A system for generating a first clock frequency for a plurality of data bursts compressed in time, the system comprising:
a transmitter for transmitting a composite stream using the data bursts clocked at a second clock frequency; and
a receiver comprising a de-multiplexer, said receiver for acquiring said composite stream, said demultiplexer comprising a phase locked loop for generating the first clock frequency based at least in part on a number of audio pixels per line and said second clock frequency.
2. The system of claim 1 , wherein said second clock frequency is higher than the first clock frequency.
3. The system of claim 1 , wherein said de-multiplexer outputs the data bursts at the first clock frequency.
4. The system of claim 1 , wherein said de-multiplexer includes a FIFO circuit.
5. The system of claim 1 wherein said phase locked loop comprises a digital phase locked loop.
6. The system of claim 5 , wherein said digital phase locked loop comprises a second order feedback loop.
7. The system of claim 6 , wherein said second order feedback loop comprises a half period calculator circuit.
8. A system for generating a first clock frequency for a plurality of data bursts compressed in time, the system comprising:
a transmitter for transmitting a composite stream using the data bursts clocked at a second clock frequency; and
a receiver comprising a de-multiplexer, said receiver for acquiring said composite stream, and said de-multiplexer comprising at least a second order feedback loop for determining a period of the first clock frequency, based at least in part on a number of audio pixels per line.
9. The system of claim 8 , wherein said second clock frequency is higher than the first clock frequency.
10. The system of claim 8 , wherein said de-multiplexer outputs the data bursts at the first clock frequency.
11. The system of claim 8 , wherein said de-multiplexer comprises a FIFO circuit.
12. A system for generating a first clock frequency for a plurality of data bursts compressed in time, the system comprising:
a transmitter for transmitting a composite stream using the data bursts clocked at a second clock frequency; and
a receiver comprising a de-multiplexer, said receiver for acquiring said composite stream, and said de-multiplexer comprising at least a half period calculator circuit for generating at least one full cycle of the first clock frequency based at least in part on the number of audio pixels per line.
13. The system of claim 12 , wherein said second clock frequency is higher than the first clock frequency.
14. The system of claim 12 , wherein said de-multiplexer outputs the data bursts at the first clock frequency.
15. The system of claim 12 , wherein said de-multiplexer comprises a FIFO circuit.
16. A method of generating a first clock frequency for a plurality of data bursts compressed in time, the method comprising:
acquiring a composite stream including at least the data bursts clocked at a second clock frequency;
generating the first clock frequency based at least in part on the number of audio pixels per line using a digital phase locked loop and said second clock frequency.
17. The method of claim 16 comprising transmitting said composite stream using the data bursts clocked at said second clock frequency.
18. The method of claim 16 , wherein said second clock frequency is higher than the first clock frequency.
19. The method of claim 16 comprising outputting the data bursts at the first clock frequency.
20. The method of claim 16 , wherein said digital phase locked loop comprises a second order feedback loop.
21. The system of claim 20 , wherein said second order feedback loop comprises a half period calculator circuit.
22. The method of claim 16 , wherein said second order feedback loop comprises a half period calculator circuit.
23. A method of generating a first clock frequency for a plurality of data bursts compressed in time, the method comprising:
transmitting a composite stream and the data bursts clocked at a second clock frequency;
acquiring said composite stream; and
generating the first clock frequency based at least in part on the number of audio pixels per line, using a de-multiplexer, said de-multiplexer having a digital phase locked loop that generates the first clock frequency using said second clock frequency.
24. The method of claim 23 , wherein said second clock frequency is higher than the first clock frequency.
25. The method of claim 23 comprising outputting the data bursts at the first clock frequency.
26. The method of claim 23 , wherein said digital phase locked loop comprises a second order feedback loop.
27. The method of claim 26 , wherein said second order feedback loop comprises a half period calculator circuit.
28. A method of generating a first clock frequency for a plurality of data bursts compressed in time, the method comprising:
acquiring a composite stream using the data bursts clocked at a second clock frequency; and
generating at least one full cycle of the first clock frequency using at least a half period calculator circuit and said second clock frequency; and
wherein the first frequency is determined based at least in part on the number of audio pixels per line.
29. The method of claim 28 comprising transmitting said composite stream using the data bursts clocked at said second clock frequency.
30. The method of claim 28 , wherein said second clock frequency is higher than the first clock frequency.
31. The method of claim 28 comprising outputting the data bursts at the first clock frequency.