Multi-bit magnetic memory cells
View Patent ↗A magnetic memory cell includes first and second magneto-resistive devices connected in series. The first and second magneto-resistive devices have sense layers with different coercivities. Magnetic Random Access Memory (MRAM) devices may include arrays of these memory cells.
1. A magnetic memory cell comprising first and second magneto-resistive devices connected in series, the first magneto-resistive device having a first sense layer, the second magneto-resistive device having a second sense layer, the first and second sense layers having different coercivities and at least one of having different sizes and different material compositions.
2. The memory cell of claim 1 , wherein the first and second devices are magnetic tunnel junctions.
3. The memory cell of claim 1 , wherein the sense layers in the first and second devices have different shapes.
4. The memory cell of claim 1 , wherein the sense layers in the first and second devices have different sizes.
5. The memory cell of claim 1 , wherein the sense layers of the first and second devices have different shapes and sizes.
6. The memory cell of claim 1 , wherein the sense layers of the first and second devices have different thicknesses.
7. The memory cell of claim 1 , wherein the sense layers of the first and second devices are made of different materials.
8. The memory device of claim 1 , wherein the first and second devices have distinguishably different delta resistances, whereby the memory cell has at least four distinguishable logic states.
9. A magnetic memory cell comprising first and second magnetic tunnel junctions connected in series, the first magnetic tunnel junction having a first sense layer, the second magnetic tunnel junction having a second sense layer, the first and second sense layers having different coercivities, the first and second magnetic tunnel junctions sharing a pinned layer.
10. The memory cell of claim 9 , wherein the first magnetic tunnel junction includes the first sense layer and a first pinned layer; and wherein the second magnetic tunnel junction includes the second sense layer end a second pinned layer.
11. The memory cell of claim 9 , wherein the sense layers of the first and second devices are back to back; and wherein the sense layers are separated by a layer of non-magnetic material.
12. The memory cell of claim 9 , wherein hysteresis loops of the first and second junctions are nested.