High performance equalizer having reduced complexity
View Patent ↗An apparatus and method for implementing an equalizer which combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP) equalizer (or a maximum likelihood sequence estimator, MLSE) to provide an equalization device with significantly lower complexity than a full-state MAP device, but which still provides improved performance over a conventional DFE. The equalizer architecture includes two DFE-like structures, followed by a MAP equalizer. The first DFE forms tentative symbol decisions. The second DFE is used thereafter to truncate the channel response to a desired memory of L 1 symbols, which is less than the total delay spread of L symbols of the channel. The MAP equalizer operates over a channel with memory of L 1 symbols (where L 1 <=L), and therefore the overall complexity of the equalizer is significantly reduced.
1. A reduced-state complexity equalizer apparatus for use with communication systems requiring equalization of a received signal subject to intersymbol interference (ISI), the apparatus comprising:
a first decision feedback equalizer device which utilizes coefficients derived from an estimated channel response of a channel and forms tentative symbol decisions;
at least a second decision feedback equalizer device which utilizes coefficients derived from the estimated channel response and the tentative symbol decisions from the first decision feedback equalizer to truncate a channel response of the channel to a desired channel memory; and
at least one non-linear equalizer device for providing equalization of the truncated channel response over the desired memory,
whereby overall complexity of the equalizer is reduced by reducing an effective delay spread of the channel.
2. The reduced-state complexity equalizer apparatus of claim 1 , wherein the non-linear equalizer device includes a maximum-a-posterori (MAP) equalizer device.
3. The reduced-state complexity equalizer apparatus of claim 1 , wherein the non-linear equalizer device includes a maximum likelihood sequence estimator (MLSE) equalizer device.
4. The reduced-state complexity equalizer apparatus of claim 1 , wherein the first decision feedback equalizer device includes a feed-forward filter and a feedback filter, and at least one second decision feedback equalizer device that includes a feedback filter.
5. The reduced-slate complexity equalizer apparatus of claim 4 , wherein coefficients of the feedback filter of the second decision feedback equalizer device comprise a subset of those of the feedback filter of the first decision feedback equalizer device.
6. The reduced-state complexity equalizer apparatus of claim 4 , wherein post-cursor interference is subtracted from an output of the feed-forward filter in the first decision feedback equalizer device and a hard symbol decision is made on this output.
7. The reduced-state complexity equalizer apparatus of claim 4 , wherein the second decision feedback equalizer device constructs partial post-cursor interference using the tentative decision from the first decision feedback equalizer, and subtracts the partial post-cursor interference from an output of the feed-forward filter.
8. The reduced-state complexity equalizer apparatus of claim 1 , wherein an output from the second decision feedback equalizer is provided as input to the non-liner equalizer device.
9. A method far reducing complexity of an equalizer for use with a communication system requiring equalization of a received incoming signal subject to intersymbol interference (ISI), the method comprising the steps of:
deriving feedback and feed-forward coefficients for associated feedback and feed-forward filters of a first and at least one subsequent decision feedback equalizer from an estimated channel response of a channel
utilizing the first decision feedback equalizer to form tentative decisions regarding certain symbols;
utilizing at least, one subsequent decision feedback equalizer to truncate the channel response to a desired memory; and
utilizing at least one non-linear equalizer for providing equalization of the truncated channel response over the desired memory,
whereby overall complexity of the equalizer is reduced by reducing an effective delay spread of the channel.
10. The method for reducing the complexity of an equalizer of claim 9 , wherein the non-linear equalizer includes a maximum-a-posterori (MAP) equalizer device.
11. The method for reducing the complexity of an equalizer of claim 9 , wherein the non-linear equalizer includes a maximum likelihood sequence estimator (MLSE) equalizer.
12. The method for reducing the complexity of an equalizer of claim 9 , wherein the step of utilizing the first decision feedback equalizer includes reconstructing post-cursor interference using decisions made on previously detected symbols, subtracting the post-cursor interference from an output of the feed-forward filter, and making a hard symbol decision on this output.
13. The method for reducing the complexity of an equalizer of claim 9 , wherein a further step of utilizing the second decision feedback equalizer includes: reconstructing partial post-cursor interference using the bard symbol decision from the first decision feedback equalizer and subtracting the partial post-cursor interference from an output of the feed-forward filter to obtain an output of the second decision feedback equalizer.
14. The method for reducing the complexity of an equalizer of claim 13 , wherein a further step of utilizing the non-linear equalizer includes: providing the output from the second decision feedback equalizer as an input to the non-linear equalizer.