Heterogeneous composite semiconductor structures for enhanced oxide and air aperture formation for semiconductor lasers and detectors and method of manufacture
View Patent ↗The present invention creates oxide and air apertures in material systems, such as InP, that do not usually accommodate epitaxial incorporation of highly oxidizing materials, such as AlAs, of sufficient thickness to adequately provide optical as well as current aperturing. A composite structure of relatively slowly oxidizing layer or layers (e.g. AlInAs on InP) with a faster-oxidizing layer or layers (e.g. AlAs on InP) can be used to produce oxide and air apertures of various shapes and sizes, and to also increase the oxidation rate.
1. A semiconductor structure comprising:
a III–V semiconductor substrate;
an aperture layer comprising at least one faster-oxidizing layer adjacent to at least one slower-oxidizing layer, wherein an air aperture is formed in the aperture layer,
wherein the slower-oxidizing layer includes aluminum indium arsenide.
2. The semiconductor structure of claim 1 , wherein the air aperture is formed by selectively etching out a portion of the aperture layer.
3. The semiconductor structure of claim 1 , wherein the faster-oxidizing layer contains aluminum arsenide.
4. The semiconductor structure of claim 1 , wherein the air aperture is tapered.
5. A semiconductor structure comprising:
an indium phosphide (InP) substrate; and
an aperture layer comprising at least one faster-oxidizing aluminum arsenide layer adjacent to at least one slower-oxidizing aluminum indium arsenide layer, wherein an air aperture is selectively etched from semiconductor material of the aperture layer.
6. A method for forming an aperture in a semiconductor comprising:
utilizing a III–V semiconductor substrate;
depositing at least one faster-oxidizing layer adjacent to at least one slower-oxidizing layer on a substrate;
forming the aperture to a desired shape by more quickly oxidizing the at least one faster-oxidizing layer than the at least one slower-oxidizing layer; and
selectively etching out the oxide to form an air aperture.
7. The method of claim 6 , wherein the desired shape is an asymmetric taper.
8. The method of claim 6 , wherein the desired shape is a symmetric taper.
9. The method of claim 6 , wherein the desired shape is untapered.
10. The method of claim 6 , wherein the substrate comprises InP.
11. The method of claim 10 , wherein the air aperture is formed by selectively etching out the oxide.
12. The method of claim 10 , wherein the faster-oxidizing layer contains aluminum arsenide.
13. The method of claim 10 , wherein the slower-oxidizing layer includes aluminum indium arsenide.
14. A method for forming an aperture in a semiconductor comprising:
utilizing an indium phosphide (InP) substrate;
depositing at least one faster-oxidizing aluminum arsenide layer adjacent to at least one slower-oxidizing aluminum indium arsenide layer on a substrate;
forming the aperture to a desired shape by more quickly oxidizing the at least one faster-oxidizing layer than the at least one slower-oxidizing layer; and
selectively etching out the semiconductor from the faster-oxidizing layer and slower-oxidizing layer to form an air aperture.
15. A method for forming an aperture in a semiconductor comprising:
utilizing an indium phosphide (InP) substrate;
depositing at least one faster-oxidizing aluminum arsenide layer adjacent to at least one slower-oxidizing aluminum indium arsenide layer on a substrate;
forming the aperture to a desired shape by more quickly oxidizing the at least one faster-oxidizing layer than the at least one slower-oxidizing layer, wherein the desired shape is an asymmetric taper.
16. A semiconductor structure formed in a DBR of a VCSEL comprising:
alternating layers containing AlInAs and AlAs sandwiched between layers containing AlGaInAs;
a buffer layer;
an InP substrate wherein the buffer layer is sandwiched between the InP substrate and the alternating layers; and
an aperture formed in the alternating layers to form an aperture in the DBR of the VCSEL.