Patent Application
Utility
App. No. 09/964,499
· Confirmation No. 2553
Semiconductor device with multi-layer wiring and reduced capacitance and manufacturing method thereof
Abandoned -- Failure to Respond to an Office Action
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2001-09-28 | TRNA |
Transmittal of New Application | 1 | View | |
| 2001-09-28 | SPEC |
Specification | 12 | View | |
| 2001-09-28 | CLM |
Claims | 8 | View | |
| 2001-09-28 | ABST |
Abstract | 1 | View | |
| 2001-09-28 | DRW |
Drawings-only black and white line drawings | 5 | View | |
| 2001-09-28 | OATH |
Oath or Declaration filed | 3 | View |
Inventors
Kenji Saito
Tokyo, JAPAN
Kazuhiko Sanada
Tokyo, JAPAN
Classification
USPC
257/758
H10W20/495
H10P14/40
H10W20/40
H10W20/072
H10W20/46
H10W20/076
H10W70/60
H10W70/611
Prosecution
- Examiner
- CAO, PHAT X
- Art Unit
- 2814
- Docket No.
- Q64204
- Confirmation No.
- 2553
Foreign Priority
297309/2000
·
2000-09-28
·
JAPAN
Publication
- Pub. No.
- US20020036349A1
- Pub. Date
- 2002-03-28
No related applications found.
from
NEC CORPORATION
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2003-02-25
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2001-09-28
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Quick Facts
- App. No.
- 09/964,499
- Filed
- 2001-09-28
- Pub. No.
- US20020036349A1
- Examiner
- CAO, PHAT X
- Art Unit
- 2814
External Links