Circuit reduction technique for improving clock net analysis performance

1. A method for performing clock analysis on an original circuit using a transistor circuit netlist and a parasitics netlist, comprising:

generating a reduced circuit netlist partly based on the transistor circuit netlist,wherein the generating is dependent on information about clock cells in a clock signal propagation path of the original circuit;

connecting a cell within the reduced circuit netlist and parasitics netlist to at least one voltage source specified in the original circuit; and

attaching information to the cell in order to create a netlist for simulation,

wherein the netlist for simulation is used for the clock analysis on the original circuit.

2. The method of claim 1 , wherein the circuit netlist is a transistor circuit netlist.

3. The method of claim 1 , wherein the cell is a clock cell.

4. The method of claim 1 , further comprising:

reading the circuit netlist, wherein reading the circuit netlist comprises:

parsing the circuit netlist according to at least one clock cell in the clock signal propagation path; and

building a graph-oriented memory structure for the at least one clock cell, wherein the graph-oriented memory structure represents a cell structure in an input specification;

selectively removing hierarchy from the graph-oriented memory structure;

traversing the graph-oriented memory structure to build the clock signal propagation path, wherein clock pins are used as reference points for the clock signal propagation path;

selectively eliminating devices from the clock signal propagation path that have no impact on the a timing property of the clock signal propagation path; and

generating the reduced circuit netlist.

5. The method of claim 4 , further comprising:

repairing a connection broken while selectively eliminating device.

6. The method of claim 5 , wherein selectively eliminating devices and repairing the connection is dependent on a predefined rule.

7. A computer system having a timing simulation tool, comprising:

a memory; and

an integrated circuit;

wherein the timing simulation tool resides in the memory and executes instructions on the integrated circuit in order to generate a reduced transistor circuit netlist, wherein generating the reduced transistor circuit netlist is dependent on the information about clock cells in a clock signal propagation path of an original circuit.

8. The computer system of claim 7 , wherein a transistor circuit netlist is reduced to the reduced transistor circuit netlist, wherein the transistor circuit netlist and a parasitics netlist are extracted from a design layout of the original circuit, and wherein the reduced transistor circuit netlist and the parasitics netlist are used to create a netlist for simulation.

9. The computer system of claim 8 , wherein the netlist for simulation is used by the timing simulation tool to analyze clock network performance of the original circuit.

10. A software tool, comprising:

a first portion that reduces a transistor circuit netlist to a reduced transistor circuit netlist, dependent on information about clock cells in a clock signal propagation path of an original circuit;

a second portion that connects a cell within the reduced circuit netlist and a parasitics netlist to at least one voltage source specified in the original circuit; and

a third portion that attaches information to the cell in order to create a netlist for simulation;

wherein the netlist for simulation is used for clock analysis on the original circuit.

11. The software tool of claim 10 , wherein the first portion comprises:

a portion that reads the circuit netlist, wherein the portion comprises:

a portion that parses the circuit netlist according to at least one clock cell in the clock signal propagation path; and

another portion that builds a graph-oriented memory structure for the at least one clock cell, wherein the graph-oriented memory structure represents a cell structure in an input specification;

another portion that selectively removes hierarchy from the graph-oriented memory structure;

another portion that traverses the graph-oriented memory structure to build the clock signal propagation path, wherein clock pins are used as reference points for the clock signal propagation path;

another portion that selectively eliminates devices from the clock signal propagation path that have no impact on the a timing property of the clock signal propagation path; and

another portion that generates the reduced circuit netlist.

12. The simulation tool of claim 10 , wherein the simulation tool reduces the transistor circuit netlist such that nonlinear circuit properties are preserved, wherein the nonlinear circuit properties comprise electrical properties of the original circuit.