Method and apparatus for online detection and correction of faults affecting system-on-chip buses
This paper presents a methodology for designing System-On-Chip interconnection architectures providing a high level of protection from crosstalk effects. An event driven simulator enriched with fault injection capabilities is exploited to evaluate the dependability level of the system being designed. The simulation environment supports several bus coding protocols and thus designers can easily evaluate different design alternatives. To enhance the dependability level of the interconnection architecture, we propose a distributed bus guardian scheme, where dedicated hardware modules monitor the integrity of the information transmitted over the bus and provide error correction mechanisms.
1. A system comprising:
a bus;
a plurality of SOC components, each connected to the bus; and
a bus guardian connected to the bus between at least two of the SOC components;
wherein the bus guardian detects and corrects a fault that occurs on the bus between the at least two SOC components; and
wherein the distance between the bus guardian and at least one of the SOC components is such that the probability of two faults occurring on the bus between the bus guardian and SOC component is negligible.
2. A system according to claim 1 , wherein the bus guardian is placed at, or less than, a predetermined distance from the SOC components.
3. A system according to claim 1 , further comprising a plurality of bus guardians connected between at least two of the SOC components.
4. A system according to claim 3 , wherein the bus guardians are placed at, or less than, a predetermined distance from the SOC components and each other.
5. A method for distributing a bus guardian and SOC components on a bus in a system on a chip comprising:
determining a fabrication parameter of the system on a chip;
determining a distance between the bus guardian and a SOC component based on the fabrication parameter;
wherein the distance is determined such that the probability of two faults occurring on the bus between the bus guardian and SOC component is negligible.
6. A method according to claim 5 , wherein the fabrication parameter is technology used.
7. A method according to claim 5 , wherein the fabrication parameter is operating frequency.
8. A method according to claim 5 , wherein the fabrication parameter is voltage.
9. A method for distributing a bus guardian and SOC components on a bus in a system on a chip comprising:
estimating a floorplan based on a specification;
determining a distance between the bus guardian and a SOC component based on the floorplan parameter;
wherein the distance is determined such that the probability of two faults occurring on the bus between the bus guardian and SOC component is negligible.
10. A method according to claim 9 , further comprising:
performing a fault-free simulation based on the specification;
performing a simulation with fault detection based on the determined distance.