Patent Assignment
Reel/Frame 013926/0288
Assignment of Assignor's Interest
Recorded: 2003-04-11
Pages: 4
Assignor
NEC USA, INC.
Executed: 2003-04-11
Assignee
NEC CORPORATION
7-1, SHIBA 5-CHOME, MINATO-KU, TOKYO 108-01, JAPAN
Covered Properties
(59)
Switch Based Network Architecture for Ip Multicast and Integrated Services
Patent:
6,671,276 →
Application:
08/972,748 →
Handoff Control for Point to Multipoint Connections in Mobile Atm Networks
Patent:
6,643,279 →
Application:
09/145,225 →
Advanced Web Bookmark Database System
Patent:
6,725,227 →
Application:
09/184,759 →
Rrgs-Round-Robin Greedy Scheduling for Input/Output Terabit Switches
Patent:
6,618,379 →
Application:
09/206,975 →
System for Personalizing, Organizing and Managing Web Information
Patent:
6,631,496 →
Application:
09/273,808 →
Fast Round Robin Priority Port Scheduler for High Capacity Atm Switches
Patent:
6,556,571 →
Application:
09/317,964 →
Simulation Vector Generation from Hdl Descriptions for Observability-Enhanced Statement Coverage
Patent:
6,816,825 →
Application:
09/335,755 →
Pipelined Fair Packet Scheduler for High Speed Optical Switches
Application:
09/335,908 →
Ip Network Access for Portable Devices
Patent:
6,591,306 →
Application:
09/357,907 →
All Optical Display with Storage and Ir-Quenchable Phosphors
Patent:
6,760,515 →
Application:
09/359,037 →
Method and Apparatus for Personalized Multimedia Summarization Based Upon User Specified Theme
Patent:
6,751,776 →
Application:
09/369,421 →
Method for Design Validation Using Retiming
Verification Method for Combinational Loop Systems
Patent:
6,816,827 →
Application:
09/410,087 →
Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation
Patent:
6,745,160 →
Application:
09/414,815 →
Fast Error Diagnosis for Combinational Verification
Patent:
6,662,323 →
Application:
09/425,886 →
Pipelined Packet Scheduler for High Speed Optical Switches
Patent:
7,058,063 →
Application:
09/460,649 →
Document Retrieval by Information Unit
Patent:
6,847,960 →
Application:
09/461,561 →
Method for Core-Based System-Level Power Modeling Using Object-Oriented Techniques
Patent:
6,865,526 →
Application:
09/489,895 →
Method of Defining and Utilizing Logical Domains to Partition and to Reorganize Physical Domains
Patent:
6,647,381 →
Application:
09/491,525 →
Low Power Hardware/Software Partitioning Approach for Core-Based Embedded Systems
Patent:
6,622,287 →
Application:
09/521,658 →
Method and System for Segmentation, Classification, and Summarization of Video Images
Patent:
7,016,540 →
Application:
09/556,349 →
Object Code Compression Using Different Schemes for Different Instruction Types
Patent:
6,691,305 →
Application:
09/556,927 →
Peripheral Partitioning and Tree Decomposition for Partial Scan
Patent:
6,732,310 →
Application:
09/568,049 →
System for the Design of High-Performance Communication Architectures for System-on-Chips Using Communication Architecture Tuners
Patent:
6,694,488 →
Application:
09/576,955 →
Methodology for the Design of High-Performance Communication Architectures for System-on-Chips Using Communication Architecture Tuners
Patent:
6,978,425 →
Application:
09/576,956 →
System and Method for Performing Timing Analysis, Including Error Diagnosis, Signal Tracking and Clock Skew
Patent:
6,594,806 →
Application:
09/588,539 →
Property Specific Testbench Generation Framework for Circuit Design Validation by Guided Simulation
Patent:
6,975,976 →
Application:
09/693,976 →
Sat-Based Image Computation with Application in Reachability Analysis
Patent:
6,728,665 →
Application:
09/693,979 →
Focused Search Engine and Method
Low Hardware Overhead Scan Based 3-Weight Weighted Random Bist Architectures
Active Inductors Using Bipolar Silicon Transistors
Text Summarization Using Relevance Measures and Latent Semantic Analysis
Optical Luminescent Display Device
A High Performance Communication Architecture for Circuit Designs Using Probabilistic Allocation of Resources
Path Provisioning for Service Level Agreements in Differentiated Service Networks
Method and Apparatus for Adaptive Bus Coding for Low Power Deep Sub-Micron Designs
Method and Apparatus for Online Detection and Correction of Faults Affecting System-on-Chip Buses
Pipeline Scheduler with Fairness and Minimum Bandwidth Guarantee
Crosstalk Mitigation Method and System
Partition-Based Decision Heuristics for Sat and Image Computation Using Sat and Bdds
Method and System for Extending the Capabilities of Handheld Devices Using Local Resources
Creating Audio-Centric, Image-Centric, and Integrated Audio-Visual Summaries
Power Mode Based Macro-Models for Power Estimation of Electronic Circuits
Multi-ISP controlled access to IP networks, based on third-party operated untrusted access stations
Application:
10/057,914 →
Publication:
US 2002/0138635
Apparatus for Public Access Mobility Lan and Method of Operation Thereof
Per-Bin Dfe for Advanced Oqam-Based Multi-Carrier Wireless Data Transmission Systems
Feed-Forward Dc-Offset Canceller for Direct Conversion Receiver
Flexible Crossbar Switching Fabric
Non-Uniform Optical Waveband Aggregator and Deaggregator and Hierarchical Hybrid Optical Cross-Connect System
Hardware acceleration system for logic simulation
Application:
10/102,749 →
Publication:
US 2003/0105617
Re-Configurable Embedded Core Test Protocol for System-on-Chips (Soc) and Circuit Boards
Apparatus for One-Cycle Decompression of Compressed Data and Methods of Operation Thereof
Document clustering with cluster refinement and model selection capabilities
Application:
10/144,030 →
Publication:
US 2003/0154181
Active Double-Balanced Mixer
Method of Image Segmentation for Object-Based Image Retrieval
Efficient Approaches for Bounded Model Checking
Method and Apparatus for Efficient Register-Transfer Level (Rtl) Power Estimation
Techniques for efficient security processing
Application:
10/259,569 →
Publication:
US 2003/0142818
Hardware/Software Platform for Rapid Prototyping of Code Compression Technologies
Related Assignments
(25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Nov 18, 1997
From: BAKRE, AJAY V.; NISHIDA, TAKESHI
To: NEC USA INC.
Reel/Frame 008834/0582 →
Correction of Assignee Address, Previously Recorded at Reel 8834, Frame 0582.
Jun 1, 1998
From: BAKRE, AJAY V.; NISHIDA, TAKESHI
To: NEC USA, INC.
Reel/Frame 009238/0710 →
Assignment of Assignor's Interest
Sep 1, 1998
From: LI, JUN; ACHARYA, ARUP
To: NEC USA, INC., C&C RESEARCH LABORATORIES
Reel/Frame 009448/0137 →
Assignment of Assignor's Interest
Nov 2, 1998
From: LI, WEN-SYAN
To: NEC USA, INC.
Reel/Frame 009560/0427 →
Assignment of Assignor's Interest
Jan 15, 1999
From: RAMAMURTHY, GOPALAKRISHNAN; FAN, RUIXUE; SMILJANIC, ALEKSANDRA
To: NEC USA, INC.
Reel/Frame 009714/0429 →
Assignment of Assignor's Interest
Mar 22, 1999
From: LI, WEN-SYAN; VU, QUOC
To: NEC USA, INC.
Reel/Frame 009847/0885 →
Assignment of Assignor's Interest
Mar 22, 1999
From: LI, WEN-SYAN; VU, QUOC
To: NEC CORPORATION
Reel/Frame 009846/0977 →
Assignment of Assignor's Interest
May 25, 1999
From: SHAHIRER, SHARIF M.; ISHII, ALEXANDER T.
To: NEC USA, INC.
Reel/Frame 009988/0166 →
Assignment of Assignor's Interest
Jun 18, 1999
From: ASHAR, PRANAV
To: NEC USA, INC.
Reel/Frame 010047/0083 →
Assignment of Assignor's Interest
Jun 18, 1999
From: CAVENDISH, DIRCEU GALVAO
To: NEC USA, INC.
Reel/Frame 010045/0691 →
Assignment of Assignor's Interest
Jun 18, 1999
From: DEVADAS, SRINIVAS; FALLAH, FARZAN
To: MASSACHUSETTS INSTITUTE OF TECHNOLOGY (MIT)
Reel/Frame 010047/0074 →
Assignment of Assignor's Interest
Jul 21, 1999
From: REDLICH, JENS-PETER
To: NEC USA, INC.,; NEC CORP.
Reel/Frame 010122/0884 →
Assignment of Assignor's Interest
Jul 21, 1999
From: REDLICH, JENS-PETER
To: NEC USA, INC.
Reel/Frame 010363/0719 →
Assignment of Assignor's Interest
Aug 6, 1999
From: GONG, YINHONG
To: NEC USA, INC.
Reel/Frame 010158/0948 →
Assignment of Assignor's Interest
Oct 1, 1999
From: XIA, YANG; ASHAR, PRANAV
To: NEC USA, INC.
Reel/Frame 010287/0503 →
Assignment of Assignor's Interest
Oct 25, 1999
From: ASHAR, PRANAV; GUPTA, AARTI
To: NEC USA, INC.
Reel/Frame 010343/0550 →
Re-Record to Correct Error in Inventor's Name at Reel 010158,Frame 0948
Nov 10, 1999
From: GONG, YIHONG
To: NEC USA, INC.
Reel/Frame 010369/0740 →
Assignment of Assignor's Interest
Dec 22, 1999
From: ASHAR, PRANAV; RAGHUNATHAN, ANAND; BHATTACHARYA, SUBHRAJIT; GUPTA, AARTI
To: NEC USA, INC.
Reel/Frame 010459/0875 →
Assignment of Assignor's Interest
Feb 3, 2000
From: CAVENDISH, DIRCEU G.
To: NEC USA, INC.
Reel/Frame 010523/0846 →
Assignment of Assignor's Interest
Feb 15, 2000
From: LI, WEN-SYAN; CANDAN, K. SELCUK; WU, YI-LEH
To: NEC USA, INC
Reel/Frame 010607/0738 →
Mortgage
Mar 8, 2000
From: HENKEL, JOERG
To: NEC USA, INC.
Reel/Frame 010661/0678 →
Assignment of Assignor's Interest
Mar 9, 2000
From: GUPTA, AARTI; ASHAR, PRANAV; MALIK, SHARAD
To: NEC USA, INC.
Reel/Frame 010604/0898 →
Assignment of Assignor's Interest
Apr 21, 2000
From: LEKATSAS, HARIS; WOLF, WAYNE
To: PRINCETON UNIVERISTY
Reel/Frame 010764/0107 →
Assignment of Assignor's Interest
Apr 21, 2000
From: HENKEL, JORG
To: NEC USA, INC.
Reel/Frame 010764/0135 →
Assignment of Assignor's Interest
Apr 24, 2000
From: GONG, YIHONG; LIU, XIN
To: NEC USA, INC.
Reel/Frame 010767/0228 →