Re-configurable embedded core test protocol for system-on-chips (SOC) and circuit boards

1. A test system for a system on chip, wherein said system on chip has a:

plurality of cores such that at least one of said plurality of cores is adapted to use a test protocol independent of a communication fabric used in the system on chip,

wherein a test client is connected only to test inputs and test outputs of said at least one of said plurality of cores.

2. The test system of claim 1 , wherein one of said plurality of cores is adapted to use multiple test schemes.

3. The test system of claim 1 , wherein a first one of said plurality of cores and a second one of said plurality of cores are from different vendors.

4. The test system of claim 3 , wherein the test system is adapted to use a uniform system on chip-level test strategy for said plurality of cores.

5. The test system of claim 1 , wherein a first one of said plurality of cores is adapted to use a first test scheme and a second one of said plurality of cores is adapted to use a second test scheme different from said first test scheme.

6. The test system of claim 1 , wherein no delay is added to paths in the system on chip.

7. The test system of claim 1 , wherein test application time of a first one of said plurality of cores overlap a test application time of a second one of said plurality of cores.

8. A system-on-chip with an embedded test protocol architecture, said system on chip comprising:

at least one embedded core;

a communication fabric that connects said at least one embedded core;

at least one test server; and

at least one test client connected to said at least one embedded core and connected to the communication fabric;

wherein said at least one test client is connected only to test inputs and test outputs of the at least one embedded core.

9. The system on chip of claim 8 , wherein said at least one embedded core connects to the communication fabric using bus interface logic.

10. The system on chip of claim 9 , wherein the bus interface logic connects only to inputs and outputs of said at least one embedded core.

11. The system on chip of claim 8 , wherein said at least one test server is implemented as an embedded core.

12. The system on chip of claim 8 , wherein said at least one test server is implemented on an on-chip processor core.

13. The system on chip of claim 8 , wherein said at least one test client is connected only to test ports of the at least one embedded core.

14. The system on chip of claim 13 , wherein said at least one test client delivers test data to the at least one embedded core by using the test ports.

15. The system on chip of claim 8 , wherein the communication fabric is a bus.

16. The system on chip of claim 15 wherein the at least one test server operates as a sole bus master.

17. The system on chip of claim 8 wherein said at least one test server and said at least one test client are adapted to exchange information using a fixed-format packet.

18. The system on chip of claim 17 , wherein the fixed-format packet is variable sized.

19. The system on chip of claim 17 , wherein the system on chip is adapted to transmit the fixed-format packet using multiple bus transactions.

20. The system on chip of claim 17 , wherein the fixed-format packet comprises a header and a payload.

21. The system on chip of claim 20 , wherein the at least one test client treats all data received after a header as payload until the at least one test client receives another header.

22. A test client for use with a system-on-chip with an embedded test protocol, said test client comprising:

a bus interface block that generates communication signals required to plug the test client into a communication fabric of the system on chip;

a core interface block that converts test data into serial data streams; and

a controller block that interprets received test packets,

wherein said test client is connected only to test inputs and test outputs of an embedded core in the system-on-chip.

23. The test client of claim 22 , wherein the core interface block converts responses from embedded cores of the system on chip into packets.

24. The test client of claim 23 wherein the controller block further comprises a decoder for interpreting received test packets and a finite state machine that provides necessary signals to control the core interface block and the bus interface block.

25. A test system for a circuit board, wherein said circuit board has a plurality of cores such that at least one of said plurality of cores is adapted to use a test protocol independent of a communication fabric used in the circuit board

wherein a test client is connected only to test inputs and test outputs of said at least one of said plurality of cores.

26. The test system of claim 25 , wherein one of said plurality of cores is adapted to use multiple test schemes.

27. The test system of claim 25 , wherein the plurality of cores are from different vendors.

28. Test system of claim 25 , wherein the system is adapted to use a uniform circuit board-level test strategy for said plurality of cores.

29. The test system of claim 25 , wherein a first one of said plurality of cores is adapted to use a first test scheme and a second one of said plurality of cores is adapted to use a second test scheme different from said first test scheme.

30. The test system of claim 25 , wherein no delay is added to paths in the test system on chip.

31. The test system of claim 25 , wherein test application time of a first one of said plurality of cores overlap a test application time of a second one of said plurality of cores.