Methodology for the design of high-performance communication architectures for system-on-chips using communication architecture tuners

1. A method of designing a communication architecture comprising:

a) receiving a partitioned system, communication architecture topology, input traces and performance matrices;

b) analyzing and creating communication analysis graph (CAG);

c) grouping communication instances to create partitions (CP) clusters using the following sub-steps;

(c)(i) analyzing the CAG to measure impact of individual communication instance delays on system performance;

(c)(ii) measuring performance impact of an instance using sensitivity; and

(c)(iii) grouping instances having a similar impact on system performance into a same partition

d) evaluating cluster statistics related to the partitions and assigning parameter values to the partitions to form a new system with new communication architecture;

e) reanalyzing the new system and recomputing performance metrics;

f) if performance is not improved then returning to step c; and

g) if performance is improved then synthesizing CATs to realize optimized protocols.

2. The method of claim 1 wherein said sensitivity of the system performance to a communication instance is measured as follows:

perturbing an existing delay of the communication instance by a predetermined value;

traversing a transition fanout of the communication instance in the CAG;

recomputing a start and finish time of affected vertices; and

calculating changes in the system performance using recomputed finish times.

3. The method of claim 1 wherein step d is accomplished by deriving a metric that penalizes a partition having a negative impact on delays of communication events in other partitions.

4. The method of claim 3 wherein said metric is calculated as follows:

analyzing the CAG and evaluating for each partition pair CP i CP j an amount of time for which communication events that belong to CP i are delayed due to events from CP j to form delay statistics, wherein i and j are positive integer values; and

combining the delay statistics into a formula that produces an optimum parameter value assignment.

5. The method of claim 4 wherein said parameter value assignment is done using heuristics.

6. The method of claim 4 wherein said parameter value is a priority.

7. The method of claim 4 wherein said parameter value is DMA block size.

8. The method of claim 4 wherein said parameter value assignment takes into account hardware complexity of implementing the parameter.