Granted Patent
Utility
US 6,535,448
· Confirmation No. 2449
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING BIDIRECTIONAL DATA TRANSFER BETWEEN A MAIN MEMORY UNIT AND AN AUXILIARY MEMORY UNIT
Inventor:
Yoshinori Matsui
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⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2001-10-15 | TRNA |
Transmittal of New Application | 4 | View | |
| 2001-10-15 | ADS |
Application Data Sheet | 2 | View | |
| 2001-10-15 | SPEC |
Specification | 60 | View | |
| 2001-10-15 | CLM |
Claims | 3 | View | |
| 2001-10-15 | ABST |
Abstract | 1 | View | |
| 2001-10-15 | DRW |
Drawings-only black and white line drawings | 19 | View | |
| 2001-10-15 | OATH |
Oath or Declaration filed | 2 | View |
Inventors
Yoshinori Matsui
Tokyo, JAPAN
Attorneys & Agents of Record
Classification
USPC
365/227
Prosecution
- Examiner
- NGUYEN, VAN THU T
- Art Unit
- 2824
- Customer No.
- 466
- Docket No.
- OSP 8978DIV
- Confirmation No.
- 2449
Foreign Priority
11-069309
·
1999-03-15
·
JAPAN
2000-023185
·
2000-01-31
·
JAPAN
Publication
- Pub. No.
- US20020015349A1
- Pub. Date
- 2002-02-07
Patent Term Adjustment
0days
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2018-08-21
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2006-11-26
from
NEC CORPORATION
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2003-01-28
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Quick Facts
- Patent No.
- US 6,535,448
- App. No.
- 09/975,957
- Filed
- 2001-10-15
- Granted
- 2003-03-18
- Pub. No.
- US20020015349A1
- Examiner
- NGUYEN, VAN THU T
- Art Unit
- 2824
- PTA
- 0 days
External Links