Reducing leakage currents in memories with phase-change material
View Patent ↗A memory cell including a phase-change material may have reduced leakage current. The cell may receive signals through a buried wordline in one embodiment. The buried wordline may include a sandwich of a more lightly doped N type region over a more heavily doped N type region over a less heavily doped N type region. As a result of the configuration of the N type regions forming the buried wordline, the leakage current of the buried wordline to the substrate under reverse bias conditions may be significantly reduced.
1. A memory cell comprising:
a substrate;
a phase-change material over said substrate;
a buried line of a first conductivity type formed in said substrate, said buried line including a more lightly doped region over a more heavily doped region and a more lightly doped region under said more heavily doped region;
a region of a second conductivity type opposite said first conductivity type over said line and under said phase-change material; and
a pair of trenches on either side of said buried line extending past said buried line and said region of a second conductivity type into said substrate under said buried line.
2. The memory cell of claim 1 including a dielectric material defining a pore over the substrate, said phase-change material being formed in said pore.
3. The memory cell of claim 2 including a contact layer under said dielectric layer aligned with said pore.
4. The memory cell of claim 3 wherein said lightly doped regions reduce the reverse bias leakage of said line.
5. The memory cell of claim 1 wherein said line is a wordline that couples to other memory cells.
6. The memory cell of claim 1 wherein said lightly doped regions are N-type material.
7. The memory cell of claim 6 wherein said lightly doped regions are N-regions.
8. The memory cell of claim 7 wherein said substrate is a P-type substrate.
9. The memory cell of claim 2 wherein said pore is lined with a sidewall spacer.
10. An electronic device comprising:
a system memory circuit including:
a substrate;
a phase-change material over said substrate;
a conductive line of a first conductivity type in said substrate, said line including a more heavily doped region sandwiched between more lightly doped regions, said conductive line providing signals to said phase-change material;
a region of a second conductivity type between said phase-change material and said conductive line;
a pair of trenches on either side of said buried line, said trenches extending through said substrate along said conductive line and said region of a second conductivity type into the substrate below said conductive line; and
a processor coupled to said system memory circuit.
11. The device of claim 10 wherein said phase-change material forms a memory cell of a storage.
12. The device of claim 11 wherein said storage is part of a computer.
13. The device of claim 11 including a processor, an interface and a bus coupled to said storage.
14. The device of claim 11 wherein said conductive line is a buried wordline.
15. The device of claim 14 including a conductive material between said phase-change material and said conductive line.
16. The device of claim 15 wherein said conductive line is formed of a material having a first conductivity type, a material of a second conductivity type being defined in said surface over said conductive line.
17. The device of claim 16 wherein said more heavily doped region is an N+ region and said more lightly doped regions are N− regions.
18. The device of claim 10 wherein said surface includes a semiconductor substrate.
19. The device of claim 18 including an insulator material positioned over said surface and a pore being formed in said insulator material, said phase-change material being formed in said pore.