IP Library Granted Patent US 7,209,476
Granted Patent B1
US 7,209,476 · App. 09/977,604 · Granted Apr 24, 2007

Method and apparatus for input/output port mirroring for networking system bring-up and debug

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Quick Facts
Patent No.
US 7,209,476
App. No.
09/977,604
Granted
Apr 24, 2007
Kind
B1
Abstract

A networking system includes a plurality of ports, each adapted to send and receive data. A switch core has a first channel configured to receive a logical input flow from each of the plurality of input ports, and has a second channel configured to receive a raw input flow from each of the plurality of input ports. Each logical input flow is carried by its corresponding raw input flow. A plurality of port mirrors are selectable from the plurality of ports. Each of the plurality of port mirrors is configured to produce a duplicate copy of at least one of the logical input flow and the raw input flow available at a selected port.

Claims (41)

1. A networking system, comprising:

a plurality of ports, each configured to send and receive data;

a switch core having a first channel configured to receive a logical input flow data from each of the plurality of ports, and having a second channel configured to receive a raw input flow data from each of the plurality of ports, wherein each logical input flow data is carried by its corresponding raw input flow data;

a plurality of port mirrors selectable from the plurality of ports, wherein each of the plurality of port mirrors is configured to provide a duplicate copy of at least one of the logical input flow data and the raw input flow data available at a selected port; and

wherein each of the plurality of ports includes a switch configured to receive an output of the switch core and configured to separate the logical input flow data from the raw input flow data.

2. The networking system of claim 1 , wherein the switch core is configured to provide multicast connections between an input node and a plurality of output nodes.

3. The networking system of claim 2 , wherein each of the plurality of ports comprises:

an ingress channel configured to send input flow data to the switch core;

an egress channel configured to receive output flow data from the switch core; and

a multiplexer configured to provide raw input flow to at least one of the switch core and the egress channel.

4. The networking system of claim 3 , wherein the switch core comprises a cross bar switch.

5. The networking system of claim 3 , wherein the switch core comprises a semiconductor chip.

6. The network system of claim 3 , wherein the switch core comprises a computer-readable medium having computer-executable instructions.

7. The networking system of claim 3 , comprising a scheduling circuit, wherein the scheduling circuit is configured to establish a set of connections for each of a plurality of output nodes allowing data to be passed from at least one of the first channel and the second channel over each of the established set of connections.

8. The networking system of claim 3 , comprising:

an input queue configured to hold a plurality of logical traffic units of the logical input flow data prior to switching at the switch core.

9. A networking system comprising:

means for receiving and sending input flow data;

means for switching at least one of a raw input flow data and a logical input flow data; and

means for producing a duplicate copy of at least one of the logical input flow data and the raw input flow data available at the means for receiving and sending input flow data.

10. The networking system of claim 9 comprising:

means for holding a plurality of logical traffic units of the logical input flow data prior to switching at the switch core.

11. The networking system of claim 10 , wherein the means for receiving and sending data includes a switch configured to receive an output of the switch core and separate the logical input flow data from the raw input flow data.

12. The networking system of claim 11 , wherein the means for switching comprises a means for providing multicast connections between an input node and a plurality of output nodes.

13. The networking system of claim 11 , wherein the means for switching the logical input flow data and the raw input flow data comprises a cross bar switch.

14. A method of operation of a networking system, the method comprising:

sending and receiving data at a plurality of ports;

receiving a logical input flow data at a first channel of a switch core and a raw input flow data at a second channel of the switch core from each of the plurality of ports;

switching the logical input flow data received at the first channel and the raw input flow data received at the second channel using the switch core;

selecting a plurality of port mirrors from the plurality of ports;

generating a duplicate copy of at least one of the logical input flow data and the raw input flow data; and

providing the duplicate copy at the selected plurality of port mirrors.

15. The method of claim 14 comprising:

debugging the networking system using the duplicate copy provided at the selected plurality of port mirrors.

16. The method of claim 14 , wherein debugging the networking system includes using a test agent configured to communicate to the plurality of ports.

17. The method of claim 14 comprising:

separating the logical flow data from the raw input flow data using a switch provided at each of the plurality of ports.

18. The method of claim 17 comprising:

queuing a plurality of logical traffic units of the logical input flow data prior to switching at the switch core.

19. The method of claim 18 , wherein switching data received at the first channel and the second channel includes using a cross bar switch.

20. The method of claim 19 , wherein the cross bar switch is configured to provide multicast connections between an input node and a plurality of output nodes.

Assignments (12)
MERGER Recorded Mar 3, 2023
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; BROADCOM INTERNATIONAL PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 062952/0850 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0097. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048555/0510 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0097 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 017206 FRAME: 0666. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2016
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 038632/0662 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032851-0001) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 037689/0001 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032851/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2006
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP PTE. LTD.
Reel/Frame 017206/0666 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 29, 2003
From: REDSWITCH, INC., A WHOLLY OWNED SUBSIDIARY OF AGILENT TECHNOLOGIES INC.
To: AGILENT TECHNOLOGIES, INC.
Reel/Frame 014089/0038 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 13, 2003
From: COLLOFF, IAN; CHOU, NORMAN; SCHOBER, RICHARD L.; GIL, MERCEDES; ROJAS, EDMUNDO; XIAOYANG, ZHANG
To: AGILENT TECHNOLOGIES, INC.
Reel/Frame 014054/0534 →