Spin dependent tunneling junctions including ferromagnetic layers having flattened peaks
View Patent ↗A spin dependent tunneling (“SDT”) junction of a memory cell for a Magnetic Random Access Memory (“MRAM”) device includes a pinned ferromagnetic layer, followed by an insulating tunnel barrier and a sense ferromagnetic layer. During fabrication of the MRAM device, after formation of the pinned layer but before formation of the insulating tunnel barrier, an exposed surface of the pinned layer is flattened. The exposed surface of the pinned layer may be flattened by an ion etching process.
1. An SDT junction of a memory cell for an MRAM device, the junction comprising:
a bottom ferromagnetic layer, the bottom ferromagnetic layer having flattened peaks;
an insulating tunnel barrier atop the bottom ferromagnetic layer; and
a top ferromagnetic layer atop the insulating tunnel barrier.
2. The junction of claim 1 , wherein the flattened peaks have a valley-to-peak height difference of no more than about one nanometer.
3. The junction of claim 1 , wherein the junction has a resistance of less than about 10 KΩ-μm 2 .
4. The junction of claim 1 , wherein the top and bottom layers are AF coupled; wherein the flattened peaks tune the AF coupling to a desired level.
5. An MRAM device comprising:
an array of memory cells, each memory cell including an SDT junction, each SDT junction including a bottom ferromagnetic layer, each bottom ferromagnetic layer having an upper surface, each upper surface having a valley-to-peak height variation of no more than about one nanometer;
a plurality of word lines extending along memory cell rows of the array; and
a plurality of bit lines extending along memory cell columns of the array.
6. The device of claim 5 , wherein resistance variation of the junctions across the entire array is no more than about 4%.
7. The device of claim 5 , wherein the junctions have a resistance of less than about 10 KΩ-μm 2 .