Prescaler architecture capable of non integer division

1. A prescaler comprising:

a first circuit configured to generate a plurality of control signals in response to a first clock signal having a first frequency;

a multiplexer configured to multiplex a plurality of data signals in response to said control signals to present a second clock signal having a second frequency that is a non-integer fraction of said first frequency;

a second circuit configured to (i) generate said data signals in response to said second clock signal and (ii) present said data signals directly to said multiplexer;

a first dividing circuit configured to divide said second clock signal by a first predetermined integer to present a third clock signal; and

a second dividing circuit configured to divide said third clock signal by a second predetermined integer to present a fourth clock signal.

2. The prescaler according to claim 1 , wherein said second circuit is further configured to sequence said data signals through a plurality of patterns response to said second clock signal.

3. The prescaler according to claim 1 , wherein said second circuit is further configured to present said data signals in a predetermined pattern such that said second frequency is an integer fraction of said first frequency.

4. The prescaler according to claim 1 , wherein said second circuit is further configured to present said data signals in a predetermined pattern such that said second frequency equals said first frequency.

5. The prescaler according to claim 1 , further comprising a plurality of latches configured to latch said data signals presented by said second circuit, wherein said second circuit presents said data signals directly to said latches instead of said multiplexer.

6. The prescaler according to claim 5 , wherein said latches are further configured to sample said data signals in a staggered order in response to said control signals.

7. The prescaler according to claim 1 , wherein said first circuit is further configured to present one of said control signals in an active state at a time.

8. The prescaler according to claim 1 , wherein said first circuit is further configured to present at least two of said control signals in an active state at a time.

9. The prescaler according to claim 1 , further comprising a selection circuit configured to control said fourth clock signal.

10. A method of dividing a first clock signal having a first frequency, the method comprising the steps of:

(A) generating a plurality of control signals in response to said first clock signal;

(B) multiplexing a plurality of data signals in response to said control signals to present a second clock signal having a second frequency that is a non-integer fraction of said first frequency;

(C) generating said data signals in response to said second clock signal;

(D) presenting said data signals directly to said multiplexing;

(E) dividing said second clock signal by a first predetermined integer to present a third clock signal: and

(F) dividing said third clock signal by a second predetermined integer to present a fourth clock signal.

11. The method according to claim 10 , further comprising the step of sequencing said data signals through a plurality of patterns response to said second clock signal.

12. The method according to claim 10 , further comprising the step of presenting said data signals to said multiplexing in a predetermined pattern such that said second frequency is an integer fraction of said first frequency.

13. The method according to claim 10 , further comprising the step of presenting said data signals to said multiplexing in a predetermined pattern such that said second frequency equals said first frequency.

14. The method according to claim 10 , further comprising the step of latching said data signals in response to generating said data signals, wherein step (D) presents said data signals directly, to said latching instead of said multiplexing.

15. The method according to claim 14 , wherein the step of latching further comprises the sub-step of sampling said data signals in a staggered order in response to said control signals prior to multiplexing.

16. The method according to claim 10 , wherein the step of generating said plurality of control signals comprises the sub-step of presenting one of said control signals in an active state at a time.

17. The method according to claim 10 , wherein the step of generating said plurality of control signals comprises the sub-step of presenting at least two of said control signals in an active state at a time.

18. The method according to claim 10 , further comprising the step of:

gating said second clock signal in response to said third clock signal and said fourth clock signal prior to generating said data signals.

19. A prescaler comprising:

means for generating a plurality of control signals in response to a first clock signal having a first frequency;

means for multiplexing a plurality of data signals in response to said control signals to present a second clock signal having a second frequency that is a non-integer fraction of said first frequency;

means for generating said data signals in response to said second clock signal;

means for dividing said second clock signal by a first predetermined integer to present a third clock signal; and

means for dividing said third clock signal by a second predetermined integer to present a fourth clock signal.

20. A prescaler comprising:

a first circuit configured to generate a plurality of control signals in response to a first clock signal having a first frequency;

a multiplexer configured to multiplex a plurality of data signals in response to said control signals to present a second clock signal having a second frequency that is a non-integer fraction of said first frequency;

a second circuit configured to generate said data signals in response to said second clock signal;

a first dividing circuit configured to divide said second clock signal by a first predetermined integer to present a third clock signal;

a second dividing circuit configured to divide said third clock signal by a second predetermined integer to present a fourth clock signal;

a gating circuit configured to gate said second clock signal received by said second circuit in response to said third clock signal and said fourth clock signal; and

a selection circuit configured to control said fourth clock signal to select a modulus of division of said first clock signal.

21. The prescaler according to claim 1 , further comprising:

a gating circuit configured to gate said second clock signal received by said second circuit in response to said third clock signal and said fourth clock signal.

22. The method according to claim 10 , further comprising the step of:

controlling said fourth clock signal to select a modulus of division of said first clock signal.