Time delay estimation in a transmitter
View Patent ↗In an embodiment, a transmitter section for a mobile device includes a predistorter for predistorting an input signal input to a modulation section. Predistortion values may be selected from a look-up table in response to a fed back signal from the output of the modulation section. A delay between the input signal and the fed back signal may be determined in two stages: a coarse delay estimation for determining a whole number of sample cycles, and a fine delay estimation for determining a fraction of a sample cycle to be added to the coarse delay estimation value.
1. A method comprising:
calculating a first delay value representing an estimated delay between an input signal and a fed back signal, said first delay value comprising a whole number of sample cycles;
calculating a second delay value from said first delay value, said second delay value comprising a fraction of a sample cycle; and
adding the first delay value and the second delay value to generate a third delay value representing a more precise estimated delay between the input signal and the fed back signal.
2. The method of claim 1 , wherein said calculating the first delay value comprises oversampling the input signal.
3. The method of claim 2 , wherein the input signal is oversampled at a sampling rate of thirty-two samples per symbol, and wherein the first delay value comprises a whole number between one and thirty-two.
4. The method of claim 2 , wherein said calculating the first delay value further comprises solving the equation:
D
=
arg
max
d
{
Corr
(
V
m
(
t
-
d
)
,
V
f
(
t
)
)
}
where
Corr
(
V
m
(
t
)
,
V
f
(
t
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)
=
C
(
n
)
=
1
N
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∑
n
=
d
+
1
N
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1
V
m
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n
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V
f
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(
n
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where D is the first delay value, V m is the input signal, and V f is the fed back signal.
5. The method of claim 1 , wherein said calculating the second delay value comprises solving the equation
a
=
-
∑
t
=
1
N
Z
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(
t
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X
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t
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+
Z
(
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X
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∑
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{
Z
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∑
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Z
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where
Z ( t )≡ K[V m ( t−D −1)− V m ( t−D )]
where
X ( t )≡ V f ( t )− KV m ( t−D −1)
where K is the linear gain factor, D is the first delay value, V m is the input signal, and V f is the fed back signal.
6. The method of claim 1 , further comprising decrementing the first delay value by one and recalculating the second delay value with the decremented first delay value in response to the second delay value being less than one.
7. The method of claim 1 , further comprising incrementing the first delay value by one and recalculating the second delay value with the incremented first delay value in response the to the second delay value being greater than one.
8. The method of claim 1 , further comprising modulating the input signal for transmission from a Personal Digital Communications (PDC) transmitter.
9. The method of claim 8 , further comprising calculating the first delay value in two slots.
10. The method of claim 8 , further comprising calculating the second delay value in four slots.
11. An apparatus comprising:
a modulation path having an input operative to receive an input signal, said modulation path operative to modulate said input signal and output a modulated signal for transmission;
a feedback path operative to generate a feedback signal from the modulated signal; and
a predistorter connected between the feedback path and the input of the modulation path, said predistorter comprising a delay estimator operative to
calculate a first delay value representing an estimated delay between the input signal and the feedback signal, said first delay value comprising a whole number of sample cycles,
calculate a second delay value from said first delay value, said second delay value comprising a fraction of a sample cycle, and
add the first delay value and the second delay value to generate a third delay value representing a more precise estimated delay between the input signal and the feedback signal.
12. The apparatus of claim 11 , further comprising a look-up table connected between the predistorter and the input of the modulation path, said look-up table including a plurality of predistortion values.
13. The apparatus of claim 12 , further comprising a PDC transmitter section.
14. The apparatus of claim 12 , wherein the lock-up table comprises a 256×2 array.
15. The apparatus of claim 12 , wherein the predistorter is operative to generate the first delay value within two slots.
16. The apparatus of claim 12 , wherein the predistorter is operative to generate the second delay value within four slots.
17. A article comprising a machine-readable medium which stores machine-executable instructions, the instructions causing a machine to:
calculate a first delay value representing an estimated delay between an input signal and a fed back signal, said first delay value comprising a whole number of sample cycles;
calculate a second delay value from said first delay value, said second delay value comprising a fraction of a sample cycle; and
add the first delay value and the second delay value to generate a third delay value representing a more precise estimated delay between the input signal and the fed back signal.
18. The article of claim 17 , wherein the instructions causing the machine to calculate the first delay value comprise instructions causing the machine to oversample the input signal.
19. The article of claim 18 , wherein the input signal is oversampled at a sampling rate of thirty-two samples per symbol, and wherein the first delay value comprises a whole number between one and thirty-two.
20. The article of claim 18 , wherein the instructions causing the machine to calculate the first delay value further comprise instructions causing the machine to solve the equation:
D
=
arg
max
d
{
Corr
(
V
m
(
t
-
d
)
,
V
f
(
t
)
)
}
where
Corr
(
V
m
(
t
)
,
V
f
(
t
)
)
=
C
(
n
)
=
1
N
-
d
∑
n
=
d
+
1
N
-
1
V
m
(
n
-
d
)
V
f
*
(
n
)
where D is the first delay value, Vm is the input signal, and Vf is the fed back signal.
21. The article of claim 17 , wherein the instructions causing the machine to calculate the second delay value further comprise instructions causing the machine to solve the equation:
a
=
-
∑
t
=
1
N
Z
*
(
t
)
X
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t
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+
Z
(
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X
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2
∑
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Z
(
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=
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{
Z
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(
t
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X
(
t
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}
∑
t
=
1
N
Z
(
t
)
2
where
Z ( t )≡ K[V m ( t−D −1)− V m ( t−D )]
where
X ( t )≡ V f ( t )− KV m ( t−D −1)
where K is the linear gain factor, D is the first delay value, Vm is the input signal, and Vf is the fed back signal.
22. The article of claim 17 , further comprising instructions causing the machine to decrement the first delay value by one and recalculate the second delay value with the decremented first delay value in response to the second delay value being less than one.
23. The article of claim 17 , further comprising instructions causing the machine to increment the first delay value by one and recalculate the second delay value with the incremented first delay value in response to the second delay value being greater than one.
24. The article of claim 17 , further comprising instructions causing the machine to modulate the input signal for transmission from a Personal Digital Communications (PDC) transmitter.
25. The article of claim 24 , further comprising instructions causing the machine to calculate the first delay value in two slots.
26. The article of claim 24 , further comprising instructions causing the machine to calculate the second delay value in four slots.
27. A system comprising:
an antenna;
a modulation path having an input operative to receive an input signal, said modulation path operative to modulate said input signal and output a modulated signal for transmission from the antenna;
a feedback path operative to generate a feedback signal from the modulated signal; and
a predistorter connected between the feedback path and the input of the modulation path, said predistorter comprising a delay estimator operative to
calculate a first delay value representing an estimated delay between the input signal and the feedback signal, said first delay value comprising a whole number of sample cycles,
calculate a second delay value from said first delay value, said second delay value comprising a fraction of a sample cycle, and
add the first delay value and the second delay value to generate a third delay value representing a more precise estimated delay between the input signal and the feedback signal.
28. The system of claim 27 , further comprising a look-up table connected between the predistorter and the input of the modulation path, said look-up table including a plurality of predistortion values.
29. The system of claim 28 , further comprising a PDC transmitter section.
30. The system of claim 28 , wherein the predistorter is operative to generate the first delay value within two slots.
31. The system of claim 28 , wherein the predistorter is operative to generate the second delay value within four slots.