IP Library Assignment 018515/0817
Patent Assignment
Reel/Frame 018515/0817

Assignment of Assignor's Interest

Recorded: 2006-11-15 Pages: 47
Assignor
INTEL CORPORATION
Executed: 2006-11-08
Assignee
MARVELL INTERNATIONAL LTD.
ARGYLE HOUSE, 41A CEDAR AVENUE, HAMILTON, HM 12, BERMUDA
Covered Properties (137)
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System and Method for Enhanced Piracy Protection in a Wireless Personal Communication Device
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Rake Receiver Interface
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Cipher Implementation
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Publication: US US20040131180A1
Method and Apparatus of De-Multiplexing Data
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Publication: US US20040071167A1
Configurable keys for pen-based devices
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Publication: US US20030221877A1
Method and Apparatus of Cross-Correlation
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Publication: US US20040062324A1
Storing and Transferring Simd Saturation History Flags and Data Size
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Cross Multiply and Add Instruction and Multiply and Subtract Instruction Simd Execution on Real and Imaginary Components of a Plurality of Complex Data Elements
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Method and apparatus to transfer information
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System and Apparatus for Early Fixed Latency Subtractive Decoding
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Transmitter
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Device, System and Method to Provide Different Bias Voltages and Common Tuning Voltage
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Method and Apparatus for Adapting Reference Templates
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Image Sensor Interface
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Speech Compression Method and Apparatus
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Unified Mmse Equalization and Multi-User Detection Approach for Use in a Cdma System
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Transmitter Operations for Interference Mitigation
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Dual Antenna System Having One Phase Lock Loop
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Translation Lookaside Buffer Prediction Mechanism
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Apparatus and Method for Power Optimized Replay via Selective Recirculation of Instructions
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Methods and Apparatus to Selectively Power Functional Units
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Filter for a Modulator and Methods Thereof
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Power Supply Delivery for Leakage Suppression Modes
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End-To-End Architecture for Mobile Client Jit Processing on Network Infrastructure Trusted Servers
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Remotely binding data to a user device
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Conduit-Sharing Apparatus, Systems, and Methods
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Methods and Apparatus for Performing Calculations Using Reduced-Width Data
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Inter-Processor Communication Link with Manageability Port
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Communication Access Apparatus, Systems, and Methods
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Low Power Semi-Trace Instruction/Trace Hybrid Cache with Logic for Indexing the Trace Cache Under Certain Conditions
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Physically-Tagged Cache with Virtually-Tagged Fill Buffers
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Updating Code with Validation
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Apparatus and Methods for Pronunciation Lexicon Compression
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Debugging Tool for Debugging Multi-Threaded Programs
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Caching Run-Time Variables in Optimized Code
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Apparatus and Method for Granting Concurrent Ownership to Support Heterogeneous Agents in on-Chip Busses Having Different Grant-to-Valid Latencies
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Power and/or Energy Optimized Compile/Execution
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Inversion of Scan Clock for Scan Cells
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Display controller bandwidth and power reduction
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Dual-Multiply-Accumulator Operation Optimized for Even and Odd Multisample Calculations
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Power Supply Detection Method, Apparatus, and System
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Apparatus and method for synthesized audible response to an utterance in speaker-independent voice recognition
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Device, system and method for reduced power consumption
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Look-Up Table for Transfer Function
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Loading an Internal Frame Buffer from an External Frame Buffer
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Supporting Different Instruction Set Architectures During Run Time
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Device, System and Method for Multi-Profile Wireless Communication
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State-Retentive Mixed Register File Array
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Two-Latch Clocked-Lssd Flip-Flop
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Serially Indexing a Cache Memory
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Device, System and Method of I/Q Mismatch Correction
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Distributed Ring Control Circuits for Viterbi Traceback
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Method and Apparatus to Manage Power Consumption of a Semiconductor Device
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Relatively low standby power
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Publication: US US20060145724A1
Relatively Low Standby Power
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Publication: US US20060145725A1
Method and Apparatus for Using Multiple Links at a Handheld Device
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Publication: US US20060089989A1
Method for enhancing the intelligibility of received speech in a noisy environment
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Power Saving in Communication Terminals
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Publication: US US20030058820A1
Method and apparatus for generating a quality measure target value based on channel conditions
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Publication: US US20030114179A1
Method and Apparatus for Searching for a Base Station Using an Adaptable Search Window
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Publication: US US20030134652A1
Method and Apparatus for Processing Signals Received from a Channel Having a Variable Channel Length
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Publication: US US20030210752A1
Novel Cdma Receiver Downlink Architecture for Soft-Handoff
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Wireless Communication Device and Method for Communicating in Site Selection Diversity Mode
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Wireless Communication Device and Method for Communicating in Site Selection Diversity Mode
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Least Mean Square Dynamic Cache-Locking
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Register File with Integrated Routing to Execution Units for Multi-Threaded Processors
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System and Method for Generating Bus Requests in Advance Based on Speculation States
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Method for Supporting Multiple Devices on a High Speed Physical Link
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Apparatus and Method for Arbitrating Heterogeneous Agents in on-Chip Busses
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Low-Leakage Level Shifter with Integrated Firewall and Method
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Enhancing the Intelligibility of Received Speech in a Noisy Environment
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Extracting Aligned Data from Two Source Registers Without Shifting by Executing Coprocessor Instruction with Mode Bit for Deriving Offset from Immediate or Register
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Method and Apparatus for Saturation Detection and Electronic Shutter in a Solid State Image Sensor
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Tap Connections for Circuits with Leakage Suppression Capability
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Digitally Controlling the Output Voltage of a Plurality of Voltage Sources
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Flip-Flop Having Multiple Clock Sources and Method Therefore
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Robust Low Complexity Multi-Antenna Adaptive Minimum Mean Square Error Equalizer
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Providing an Adder with a Conversion Circuit in a Slack Propagation Path
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Registering Events While Clocking Multiple Domains
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Processor and Method for Weight Detection in a Closed Loop Diversity Mode Wcdma System
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Method and Apparatus for Reducing Dc Offset in a Wireless Receiver
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Methods and Apparatus for Cache Intervention
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Methods and Apparatus for Cache Intervention
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Methods and Apparatus for Cache Intervention
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Methods and Apparatus for Transferring Cache Block Ownership
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Cyclic Regulation Apparatus, System, and Method
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Low Power Domino Tree Decoder
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Apparatus and Method for Vectorization of Detected Saturation and Clipping Operations in Serial Code Loops of a Source Program
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Snoopy Virtual Level 1 Cache Tag
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Low Power Set Associative Cache
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Hysteretic Self-Biased Amplifier
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Novel Receiver Architecture for Cdma Receiver Downlink
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Multi-Mouse Actions Stylus
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Conditional execution of coprocessor instruction based on main processor arithmeatic flags
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Multimedia corprocessor control mechanism including alignment or broadcast instructions
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Digital Regulation Circuit
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Method and Apparatus of Memory Management
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Least Mean Square Dynamic Cache-Locking
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Predecode Apparatus, Systems, and Methods
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Low Power State Retention
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Level Shifter and Voltage Translator
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Voltage Level Shifter
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System and Method for High-Speed Communications Between an Application Processor and Coprocessor
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System and Method for Generating Bus Requests in Advance Based on Speculation States
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Method and Apparatus for Measuring Accuracies of Fixed-Point Computations
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Dynamic Tlb Locking Based on Page Usage Metric
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Three-Dimensional Position Calibration of Audio Sensors and Actuators on a Distributed Computing Platform
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Large Fan-in, Dynamic, Bicmos Logic Gate
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Low-Leakage Level Shifter with Integrated Firewall and Method
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Crystal Oscillator with Variable Bias Generator and Variable Loop Filter
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Programmable State Machine Employing a Cache-Like Arrangement
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Method and Apparatus for Increasing Throughput When Accessing Registers by Using Multi-Bit Scoredboarding with a Bypass Control Unit
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Multi-Bit Scoreboarding to Handle Write-After-Write Hazards and Eliminate Bypass Comparators
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Method and Apparatus for Employing a Light Shield to Modulate Pixel Color Responsivity
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Method and apparatus for employing a light shield to modulate pixel color responsivity
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Method and Apparatus for Employing a Light Shield to Modulate Pixel Color Responsivity
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Method and Apparatus for Speeding Sequential Access of a Set-Associative Cache
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Active Digital Audio/Video Signal Modification to Correct for Playback System Deficiencies
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5-Volt Tolerant 3-Volt Drive Push-Pull Buffer/Driver
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Register File with Improved Noise Immunity and Aspect Ratio
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Method and Apparatus to Encode Digital Signals
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Tap Connections for Circuits with Leakage Suppression Capability
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Tap Connections for Circuits with Leakage Suppression Capability
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Apparatus and Circuit Having Reduced Leakage Current and Method Therefor
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Time Delay Estimation in a Transmitter
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Enhancing the Intelligibility of Received Speech in a Noisy Environment
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Electrostatic Discharge Protection Device and Method Therefor
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Using a Processor to Program a Semiconductor Memory
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Method and Apparatus for Using Duality to Remotely Communicate
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Related Assignments (5)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Jul 31, 2012
From: PICK, KOBBY; PERETS, YONA
To: D.S.P.C. TECHNOLOGIES LTD.
Reel/Frame 028691/0589 →
Assignment of Assignor's Interest Oct 17, 2012
From: MAZUZ, GADI; MARGULIS, ALEX
To: D.S.P.C. TECHNOLOGIES LTD.
Reel/Frame 029143/0686 →
Assignment of Assignor's Interest Jan 29, 2020
From: MARVELL WORLD TRADE LTD.
To: MARVELL INTERNATIONAL LTD.
Reel/Frame 051778/0537 →
Assignment of Assignor's Interest Feb 20, 2020
From: MARVELL INTERNATIONAL LTD.
To: CAVIUM INTERNATIONAL
Reel/Frame 052918/0001 →
Assignment of Assignor's Interest Jun 16, 2020
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE, LTD.
Reel/Frame 053475/0001 →