Translation lookaside buffer prediction mechanism
View Patent ↗According to one embodiment a central processing unit (CPU) is disclosed. The CPU includes a translation lookaside buffer (TLB). The TLB predicts a set index value prior to the generation of an effective address.
1. A central processing unit (CPU) comprising:
a translation lookaside buffering; and
a mapping logic function to predict a set index value for the TLB prior to the generation of an effective address, the mapping logic having a N-bit add modulo 2 N function of base-register bits and offset bits of a virtual address, where N is smaller than the number of bits in a virtual address.
2. The CPU of claim 1 wherein the mapping logic function distributes entries within the TLB throughout the TLB.
3. A central processing unit (CPU) comprising:
a translation lookaside buffering; and
a mapping logic function to predict a set index value for the TLB prior to the generation of an effective address, the mapping logic having an Exclusive- or of some number of base-register bits and some number of offset bits of a virtual address.
4. The CPU of claim 3 further comprising a register interface having one or more registers to control the TLB.
5. The CPU of claim 4 wherein the one or more registers within the register interface chooses an entry within the TLB to be accessed.
6. A central processing unit (CPU) comprising:
a translation lookaside buffering; and
a mapping logic function to predict a set index value for the TLB prior to the generation of an effective address, wherein the predicted set index may differ from the effective address without requiring recovery actions if the predicted set index and the effective address differ.
7. The CPU of claim 6 wherein mapping logic function includes a first set of bits from instruction and a second set of bits from base and offset addresses.
8. The CPU of claim 6 wherein the effective address being mapped is the address of an instruction that is being fetched for execution.
9. The CPU of claim 6 wherein the effective address being mapped is the address of data being read or written by the processor.
10. A central processing unit (CPU) comprising:
a translation lookaside buffering; and
a mapping logic function to predict a set index value for the TLB prior to the generation of an effective address, the mapping logic function includes control signals received from the processor and bits received from the generation of the effective address.
11. The CPU of claim 10 wherein the mapping logic combines the signals and the bits using a hash to predict a set to look up the translation for the predicted address.
12. A method comprising:
looking up a register at a register interface; and
predicting a set index value for a translation lookaside buffer (TLB) at a mapping logic function having an Exclusive- or of some number of base-register bits and some number of offset bits of a virtual address prior to the generation of an effective address.
13. The method of claim 12 further comprising performing a lookup of the TLB using the predicted set index.
14. The method of claim 12 further comprising calculating an effective address.
15. The method of claim 12 wherein the predicted set index differs from the effective address.
16. A computer system comprising central processing unit (CPU) having a mapping logic function to predict a set index value for a translation lookaside buffer (TLB) prior to the generation of an effective address, the mapping logic function having a N-bit add modulo 2 N function of base-register bits and offset bits of a virtual address, where N is smaller than the number of bits in a virtual address.
17. The computer system of claim 16 wherein the mapping logic function distributes entries within the TLB throughout the TLB.
18. The computer system of claim 16 wherein the mapping logic function comprises an Exclusive- or of some number of base-register bits and some number of offset bits of a virtual address.
19. The computer system of claim 16 further comprising a register interface having one or more registers to control the TLB.
20. The computer system of claim 19 wherein the one or more registers within the register interface chooses an entry within the TLB to be accessed.
21. The computer system of claim 16 wherein the mapping logic function includes control signals received from the processor and bits received from the generation of the effective address.
22. The computer system of claim 21 wherein the mapping logic combines the signals and the bits using a hash to predict a set to look up the translation for the predicted address.
23. A computer system comprising:
central processing unit (CPU) having a mapping logic function to predict a set index value for a translation lookaside buffer (TLB) prior to the generation of an effective address, the mapping logic having a N-bit add modulo 2 N function of base-register bits and offset bits of a virtual address, where N is smaller than the number of bits in a virtual address;
a chipset coupled to the CPU and
a main memory coupled to the chipset.
24. The computer system of claim 23 wherein the mapping logic function distributes entries within the TLB throughout the TLB.